US5025256A
Expired / Lapsed
US
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Data transmission code
Assignee: Fujitsu Services Ltd
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Filing: 1990-04-17
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Granted: 1991-06-18
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Expires: 2010-04-17
Abstract
Abstract An 8B:10B serial data transmission code is described, which provides an overall balance between ones and zeros, a code run bound of 4, and a worst case transition density of 40%. In addition, the code provides two special control characters which are unique in the coded bit stream and can be used for synchronization. The data can be encoded using a 256×8 ROM, and decoded using a 1024×6 ROM, with two bits being transmitted unencoded.
Inventors
- 👤 Reginald W. Stevens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:41
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/14; H03M5/145; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
194 words
A method of encoding data comprising: (I) forming a set of 10-bit code blocks satisfying the following rules: (a) each code block in the set contains either 5 bits of a first prdetermined binary value and 5 bits of a second predetermined binary value, or 4 bits of the first binary value, and 6 bits of the second binary value, (b) no code block in the set has more than 4 contiguous bits of the first binary value of more than 4 contiguous bits of the second binary value, (c) each code block in the set has at least one transition in the first three bits of the code block and at least one transition in the last three bits of the code block, (d) each code block in the set contains at least four transitions, and (e) each code block in the set contains at least two transitions in the first six bits of the code block and at least two transitions in the last six bits of the code block, (II) receiving input 8-bit data bytes; and (III) encoding each 8-bit data byte as one of said set of 10-bit code blocks.
Claim 2
Independent Claim
194 words
A method of encoding data comprising: (I) forming a set of 10-bit code blocks satisfying the following rules: (a) each code block in the set contains either 5 bits of a first prdetermined binary value and 5 bits of a second predetermined binary value, or 4 bits of the first binary value, and 6 bits of the second binary value, (b) no code block in the set has more than 4 contiguous bits of the first binary value of more than 4 contiguous bits of the second binary value, (c) each code block in the set has at least one transition in the first three bits of the code block and at least one transition in the last three bits of the code block, (d) each code block in the set contains at least four transitions, and (e) each code block in the set contains at least two transitions in the first six bits of the code block and at least two transitions in the last six bits of the code block, (II) receiving input 8-bit data bytes; and (III) encoding each 8-bit data byte as one of said set of 10-bit code blocks.
Claim 3
Dependent Claim
45 words
A method according to claim 1 wherein alternate disparate code blocks (i.e. code blocks containing 4 bits of the first binary value and 6 bits of the second binary value) are inverted to maintain an overall balance between ones and zeros in the encoded data.
Claim 4
Dependent Claim
18 words
A method according to claim 1 wherein the 10-bit blocks 1000011110 and 0111100001 are used as control characters.
Claim 5
Dependent Claim
62 words
Data encoding apparatus comprising: (a) a 256 word×8-bit memory, having an 8-bit address input and an 8-bit data output, (b) means for receiving an 8-bit input data byte and applying the input data byte to said address input, and (c) means for combining said 8-bit data output with two predetermined bits of said input data byte, to produce a 10bit code block.
Claim 6
Dependent Claim
62 words
Data encoding apparatus comprising: (a) a 256 word×8-bit memory, having an 8-bit address input and an 8-bit data output, (b) means for receiving an 8-bit input data byte and applying the input data byte to said address input, and (c) means for combining said 8-bit data output with two predetermined bits of said input data byte, to produce a 10bit code block.
Claim 7
Dependent Claim
20 words
Apparatus according to claim 4 wherein said two predetermined bits provide the third and eighth bits of said code block.
Claim 8
Dependent Claim
39 words
Apparatus according to claim 4 further comprising means for detecting disparate code blocks (i.e. blocks containing 4 bits of the first binary value and 6 bits of the second binary value) and for selectively inverting alternate disparate code blocks.
Claim 9
Dependent Claim
152 words
Apparatus according to claim 4 wherein said code blocks satisfy the following rules: (a) each code block contains either 5 bits of a first predetermined binary value and 5 bits of a second predetermined binary value, or 4 bits of the first binary value, and 6 bits of the second binary value, (b) no code block has more than 4 continguous bits of the first binary value or more than 4 contiguous bits of the second binary value, (c) each code block has at least one transition in the first three bits of the code block and at least one transition in the last three bits of the code block, (d) each code block contains at least four transitions, and (e) each code block contains at least two transitions in the first six bits of the code block and at least two transitions in the last six bits of the code block.
Claim 10
Dependent Claim
62 words
Data decoding apparatus comprising: (a) a 1024 word×6 bit memory having a 10-bit address input and a 6-bit data output, (b) means for receiving a 10-bit code block and applying the code block to said address input, and (c) means for combining said 6-bit data output with two predetermined bits of said code block to produce a decoded 8-bit data output byte.
Claim 11
Dependent Claim
62 words
Data decoding apparatus comprising: (a) a 1024 word×6 bit memory having a 10-bit address input and a 6-bit data output, (b) means for receiving a 10-bit code block and applying the code block to said address input, and (c) means for combining said 6-bit data output with two predetermined bits of said code block to produce a decoded 8-bit data output byte.
Claim 12
Dependent Claim
19 words
Apparatus according claim 8 wherein said two predetermined bits are the third and eighth bits of the code block.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |