Patent US1487975A successfully refreshed from Google Patents.
Patent US5025211A successfully refreshed from Google Patents.
US5025211A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Technique for reducing electromagnetic interference
Assignee: Nokia Bell Labs
•
Filing: 1989-12-20
•
Granted: 1991-06-18
•
Expires: 2009-12-20
Abstract
Abstract At least one pair of areas on a circuit pack or substrate is allocated for the placement of electromagnetic interference (EMI) absorbing material, e.g., split ferrite cores. All or a portion of the conductor paths for the circuit are routed between pairs of the allocated areas. After the circuit pack is developed and tested, if EMI suppression is required, the EMI-absorbing material extends around the conductors passing between the pairs of allocated areas using holes formed through the allocated pairs of areas. Such holes are formed prior to circuit assembly or, alternatively, are formed only as needed after circuit testing. A clip is used to secure the EMI-absorbing material to the circuit pack. Advantageously, the insertion and securement of the EMI-absorbing material does not require any soldering or special manufacturing tools or fixtures. Accordingly, it can be readily provided in any manufacturing process.
Inventors
- 👤 Adam B. Craft
- 👤 Gabor P. Torok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:10
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/023; H05K1/0233; G; G01; G01R; G01R1/00; G01R1/02; G01R1/18; H05K1/18; H05K1/182; H05K2201/00; H05K2201/08; H05K2201/083; H05K2201/086; H05K3/00; H05K3/30; H05K3/301
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
140 words
A method of reducing electromagnetic interference on a circuit pack including at least one conductive path formed on a circuit board having two sides, said method comprising the steps of allocating, during design of said circuit pack, at least one pair of areas on said circuit board for placement of electromagnetic interference absorbing material; routing a predetermined portion of said conductive paths between said pair of areas; fabricating said circuit pack; testing said assembled circuit pack for compliance with predetermined criteria, said testing providing either a first or a second result; and adding, only in response to a first result of said testing, electromagnetic interference absorbing material which passes through holes in certain ones of said allocated pairs of areas, said material extending from said sides, the holes being formed at any time prior to the addition of said material.
Claim 2
Independent Claim
140 words
A method of reducing electromagnetic interference on a circuit pack including at least one conductive path formed on a circuit board having two sides, said method comprising the steps of allocating, during design of said circuit pack, at least one pair of areas on said circuit board for placement of electromagnetic interference absorbing material; routing a predetermined portion of said conductive paths between said pair of areas; fabricating said circuit pack; testing said assembled circuit pack for compliance with predetermined criteria, said testing providing either a first or a second result; and adding, only in response to a first result of said testing, electromagnetic interference absorbing material which passes through holes in certain ones of said allocated pairs of areas, said material extending from said sides, the holes being formed at any time prior to the addition of said material.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said electromagnetic interference absorbing material is a ferrite material.
Claim 4
Dependent Claim
12 words
The method of claim 1 wherein said material is a split core.
Claim 5
Dependent Claim
39 words
The method of claim 1 wherein said routed conductive paths are routed so that any common mode currents in each conductive path between said pairs of areas will each contribute to a high frequency impedance in any added material.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein said routed conductors are all of said conductive paths in said circuit pack.
Claim 7
Dependent Claim
27 words
The method of claim 1 wherein said circuit pack further includes at least one connector and said pairs of allocated areas are positioned close to said connector.
Claim 8
Dependent Claim
25 words
The method of claim 1 wherein each conductive path in said predetermined portion passes between an associated pair of allocated areas a plurality of times.
Claim 9
Dependent Claim
23 words
The method of claim 1 wherein the certain ones of said allocated pairs of areas are all of said allocated pairs of areas.
Claim 10
Dependent Claim
25 words
The method of claim 1 wherein the certain ones of said allocated pairs of areas are less than all of said allocated pairs of areas.
References Cited (Backward Citations)
US3191136A
Cited
US3919638A
Cited
US4012703A
Cited
US4201965A
Cited
US4374369A
Cited
US4342976A
Cited
US4758808A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |