US5024962A
Expired / Lapsed
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Method for preventing auto-doping in the fabrication of metal gate CMOS devices
Assignee: TELCOM SUMICONDUCTOR Inc A Corp OF CALIFORNIA
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Filing: 1990-04-20
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Granted: 1991-06-18
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Expires: 2010-04-20
Abstract
Abstract A method of fabricating metal gate field effect transistors utilizing a rapid thermal oxidation process to form a sealing oxide which prevents auto-doping during the formation of the gate oxide.
Inventors
- 👤 Roger W. Murray
- 👤 Nevand Godhwani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:41
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D64/01346; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0181; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/004
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
88 words
A method of fabricating a field effect transistor in a substrate, comprising the steps of: (a) providing source and drain regions in the substrate, the source and drain regions being spaced apart to define a channel therebetween; (b) exposing the surface of the substrate overlying the channel; (c) forming a sealing oxide at the surface of the substrate overlying the channel by rapid thermal oxidation; (d) forming a gate oxide layer overlying the channel after said step (c); and (e) providing a gate overlying the gate oxide layer.
Claim 2
Independent Claim
88 words
A method of fabricating a field effect transistor in a substrate, comprising the steps of: (a) providing source and drain regions in the substrate, the source and drain regions being spaced apart to define a channel therebetween; (b) exposing the surface of the substrate overlying the channel; (c) forming a sealing oxide at the surface of the substrate overlying the channel by rapid thermal oxidation; (d) forming a gate oxide layer overlying the channel after said step (c); and (e) providing a gate overlying the gate oxide layer.
Claim 3
Dependent Claim
32 words
A method according to claim 1, wherein said step (c) comprises placing the substrate in an oxidizing environment and heating the substrate to at least 1000° C. in less than one minute.
Claim 4
Dependent Claim
32 words
A method according to claim 2, wherein said step (c) comprises placing the substrate in an oxidizing environment and heating the substrate to at least 1100° C. in less than 30 seconds.
Claim 5
Independent Claim
58 words
A method of forming a gate oxide for a metal gate field effect transistor formed in a substrate, comprising the sequential steps of: (a) oxidizing the substrate to form a sealing oxide layer having a thickness of approximately 100-150Å by rapid thermal annealing; and (b) forming the gate oxide by oxidizing the substrate to form the gate oxide.
Claim 6
Independent Claim
58 words
A method of forming a gate oxide for a metal gate field effect transistor formed in a substrate, comprising the sequential steps of: (a) oxidizing the substrate to form a sealing oxide layer having a thickness of approximately 100-150Å by rapid thermal annealing; and (b) forming the gate oxide by oxidizing the substrate to form the gate oxide.
Claim 7
Dependent Claim
26 words
A method according to claim 4, wherein said step (a) comprises oxidizing the substrate in an environment comprising oxygen for a time less than two minutes.
Claim 8
Dependent Claim
75 words
A method according to claim 4, wherein said step (b) comprises oxidizing the substrate by the sequential sub-steps of: (i) placing the substrate in an environment comprising oxygen; (ii) raising the temperature of the substrate to greater than 1100° C. in less than 30 seconds; (iii) maintaining the temperature of the substrate at greater than 1100° C. for a period sufficient to grow 100-150Å of oxide; and (iv) cooling the substrate in an inert environment.
Claim 9
Independent Claim
149 words
A method of preventing auto-doping in the fabrication of metal gate field effect transistors, comprising the steps of: (a) providing source and drain regions in a substrate, the source and drain regions being spaced apart to define a channel therebetween; (b) exposing the surface of the substrate corresponding to the position of the channel; (c) sealing the surface of the substrate exposed in said step (b) by rapid thermal oxidation, comprising the substeps of: (1) placing the substrate in an oxidizing environment and raising the temperature of the substrate to greater than --00 C in less than 20 seconds, (2) changing the environment to an inert environment and reducing the temperature of the substrate at a rate of greater than -60° C. per second; (d) oxidizing the substrate to form a gate oxide after said step (c); and (e) providing a gate overlying the gate oxide and the channel.
Claim 10
Independent Claim
149 words
A method of preventing auto-doping in the fabrication of metal gate field effect transistors, comprising the steps of: (a) providing source and drain regions in a substrate, the source and drain regions being spaced apart to define a channel therebetween; (b) exposing the surface of the substrate corresponding to the position of the channel; (c) sealing the surface of the substrate exposed in said step (b) by rapid thermal oxidation, comprising the substeps of: (1) placing the substrate in an oxidizing environment and raising the temperature of the substrate to greater than --00 C in less than 20 seconds, (2) changing the environment to an inert environment and reducing the temperature of the substrate at a rate of greater than -60° C. per second; (d) oxidizing the substrate to form a gate oxide after said step (c); and (e) providing a gate overlying the gate oxide and the channel.
Claim 11
Dependent Claim
227 words
A process of fabricating a complementary metal-oxide-silicon (CMOS) field effect transistor (FET) in a substrate having N-type conductivity, comprising the steps of: (a) providing a first oxide layer on the surface of the substrate; (b) removing a selected portion of the first oxide layer corresponding to a region where a P-well is to be formed; (c) implanting a P-type dopant in the substrate in the region where the first oxide layer has been removed to form a P-well; (d) annealing the FET to drive the dopant implanted in said step (c) and to grow a second oxide layer in the regions where the first oxide layer was removed in said step (b); (e) forming P.sup. -type source and drain regions in the substrate, the P.sup. -type source and drain regions being spread apart to define a channel therebetween; (f) forming N-type source and drain regions in the P-well, the N.sup. -type source and drain being spaced apart to define a second channel therebetween; (g) exposing portions of the surface of the substrate overlying the first and second channels; (h) rapid thermally annealing the FET for less than two minutes to form a sealing oxide; (i) oxidizing the substrate to form a gate oxide after said step (h); and (j) forming first and second gates overlying the gate oxide and respective areas of the first and second channels.
Claim 12
Dependent Claim
227 words
A process of fabricating a complementary metal-oxide-silicon (CMOS) field effect transistor (FET) in a substrate having N-type conductivity, comprising the steps of: (a) providing a first oxide layer on the surface of the substrate; (b) removing a selected portion of the first oxide layer corresponding to a region where a P-well is to be formed; (c) implanting a P-type dopant in the substrate in the region where the first oxide layer has been removed to form a P-well; (d) annealing the FET to drive the dopant implanted in said step (c) and to grow a second oxide layer in the regions where the first oxide layer was removed in said step (b); (e) forming P.sup. -type source and drain regions in the substrate, the P.sup. -type source and drain regions being spread apart to define a channel therebetween; (f) forming N-type source and drain regions in the P-well, the N.sup. -type source and drain being spaced apart to define a second channel therebetween; (g) exposing portions of the surface of the substrate overlying the first and second channels; (h) rapid thermally annealing the FET for less than two minutes to form a sealing oxide; (i) oxidizing the substrate to form a gate oxide after said step (h); and (j) forming first and second gates overlying the gate oxide and respective areas of the first and second channels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |