Semiconductor memory device having testing function and testing method thereof

Claim 2

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means and evaluation means for evaluating said operation performed by said second means.

Claim 3

A semiconductor memory device according to claim 1, wherein said test signal generating means generates said test signal when voltage of a signal applied to said external terminal is different from voltage in an ordinary operation.

Claim 4

A semiconductor memory device according to claim 2, wherein said test signal generating means comprises high voltage detection means responsive to application of voltage higher than voltage of an ordinary logical level to said external terminal for generating said test signal.

Claim 5

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detect of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said test signal generating means generates said test signal when timing of a signal applied to said external terminal is different from a timing in an ordinary operation.

Claim 6

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detect of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said test signal generating means generates said test signal when timing of a signal applied to said external terminal is different from a timing in an ordinary operation.

Claim 7

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said test signal generating means generates said test signal when voltage of a signal applied to said external terminal is different from voltage in an ordinary operation, and a timing of a signal applied to said external terminal is different from a timing in an ordinary operation.

Claim 8

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said test signal generating means generates said test signal when voltage of a signal applied to said external terminal is different from voltage in an ordinary operation, and a timing of a signal applied to said external terminal is different from a timing in an ordinary operation.

Claim 9

A semiconductor memory device according to claim 3, wherein said external terminal comprises first and second external terminals, and said test signal generating means comprises, timing detection means responsive to the fact that timing of a signal applied to said first external terminal and timing of a signal applied to said second external terminal are different from an ordinary timing for generating said test signal.

Claim 10

A semiconductor memory device according to claim 4, wherein said external terminal comprises first and second external terminals, said test signal generating means comprises, high voltage detection circuit (20) responsive to application of voltage higher than voltage of an ordinary logical level to said first external terminal for generating a predetermined signal, and timing detection means responsive to the fact that timings of signals applied to said first and second external terminals are different from an ordinary timing and said predetermined signal is applied from said high voltage detection means, for generating said test signal.

Claim 11

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said external terminal comprises first and second external terminals, and said test signal generating mean comprises, high voltage detection means responsive to application of voltage higher than that of an ordinary logical level to said first external terminal for generating a predetermined signal, and logical means responsive to application of a signal of a predetermined logical level to said second external terminal and application of said predetermined signal from said high voltage detection means for generating said test signal.

Claim 12

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said external terminal comprises first and second external terminals, and said test signal generating mean comprises, high voltage detection means responsive to application of voltage higher than that of an ordinary logical level to said first external terminal for generating a predetermined signal, and logical means responsive to application of a signal of a predetermined logical level to said second external terminal and application of said predetermined signal from said high voltage detection means for generating said test signal.

Claim 13

A semiconductor memory device according to claim 1, which further comprises, switching signal generating means responsive to a predetermined address signal for applying said test signal from said test signal generating means to said delay means.

Claim 14

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, evaluation means for evaluating said operation performed by said second means, switching signal generating means responsive to a predetermined address signal and said test signal from said test signal generating means for generating a plurality of switching signals, and wherein said delay means delays said first signal at a plurality of stages based on said plurality of switching signals.

Claim 15

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, evaluation means for evaluating said operation performed by said second means, switching signal generating means responsive to a predetermined address signal and said test signal from said test signal generating means for generating a plurality of switching signals, and wherein said delay means delays said first signal at a plurality of stages based on said plurality of switching signals.

Claim 16

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function mean for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said delay means comprise, inverting means having input terminals and output terminals, capacitance means, and switching means connected between said input terminal or said output terminal of said inverting means and said capacitance means, and being rendered nonconductive in response to said test signal.

Claim 17

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function mean for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said delay means comprise, inverting means having input terminals and output terminals, capacitance means, and switching means connected between said input terminal or said output terminal of said inverting means and said capacitance means, and being rendered nonconductive in response to said test signal.

Claim 18

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said delay means comprises, first inverting means, second inverting means provided in parallel with said first inverting means, and switching means responsive to said test signal for disabling said second inverting means.

Claim 19

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said delay means comprises, first inverting means, second inverting means provided in parallel with said first inverting means, and switching means responsive to said test signal for disabling said second inverting means.

Claim 20

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said delay means comprises, an input terminal receiving said first signal, an output terminal, first nd second transfer gates coupled in parallel between in said input terminal and said output terminal, and delay circuits coupled between said first transfer gate and said input terminal or said output terminal, said second transfer gate being rendered conductive in response to said test signal.

Claim 21

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, second function means for performing an operation in response to said second signal outputted from said delay means, and evaluation means for evaluating said operation performed by said second means, wherein said delay means comprises, an input terminal receiving said first signal, an output terminal, first nd second transfer gates coupled in parallel between in said input terminal and said output terminal, and delay circuits coupled between said first transfer gate and said input terminal or said output terminal, said second transfer gate being rendered conductive in response to said test signal.

Claim 22

A semiconductor memory device according to claim 10, wherein said delay means comprises, inverting means having an input terminal and an output terminal, a plurality of capacitance means, and switching means connecting or non-connecting any of said plurality of capacitance means to an internal terminal or an output terminal of said inverting means based on said plurality of switching signals from said switching signal generating means.

Claim 23

A semiconductor memory device according to claim 1, which further comprises, a memory cell array including a plurality of bit line pairs, a plurality of word lines arranged so as to intersect with said plurality of bit line pairs, and a plurality of memory cells provided at intersections between said plurality of bit line pairs and said plurality of word lines, a plurality of sense amplifier amplifying potential difference on said plurality of bit line pairs an address buffer receiving an address signal from the external, input/output line pair an X decoder receiving an address signal from said address buffer, and selecting any of said plurality of word lines, a Y decoder receiving an address signal from said address buffer, selecting any of said plurality of bit line pairs and connecting the selected bit line pairs to said input/output line pair an output amplifier amplifying a signal on said input/output line pair, a word line driving signal generating circuit responsive to a predetermined control signal for applying a word line driving signal to said X decoder, a sense amplifier driving signal generating circuit responsive to said word line driving signal for applying a sense amplifier activating signal to said plurality of sense amplifiers, a decoder driving signal generating circuit responsive to a predetermined signal for applying a decoder driving signal to said Y decoder, and an output amplifier driving signal generating circuit responsive to said decoder driving signal for applying an output amplifier driving signal said output amplifier.

Claim 24

A semiconductor memory device according to claim 15, wherein said first function means is said X decoder, said delay means is said sense amplifier driving signal generating circuit, and said second function means and said evaluation means are comprised of said plurality of sense amplifiers.

Claim 25

A semiconductor memory device according to claim 15, wherein said first function means is said address buffer said delay means is said word line driving signal generating circuit, said second function means is said X decoder and said evaluation means is comprised of said plurality of memory cells and said plurality of sense amplifier.

Claim 26

A semiconductor memory device according to claim 15, wherein said first function means is said Y decoder, said delay means is said output amplifier driving signal generating circuit, and said second function means and said evaluation means are comprised of said output amplifier.

Claim 27

A semiconductor memory device according to claim 15, wherein said first function means is said address buffer said delay means is said decoder driving signal generating circuit, said second function means is said Y decoder, and said evaluation means is comprised of said plurality of memory cells and said output amplifier.

Claim 28

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving in said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, and evaluation means for evaluating said operation performed by said second means.

Claim 29

A semiconductor memory device having an external terminal and operating in response to a signal applied to the external terminal, and including a circuit for facilitating detection of a defect in said memory device, said circuit comprising: test signal generating means responsive to application of a signal of a predetermined state different from a state of an ordinary operation for generating a test signal, first function means for performing an operation in response to a predetermined first signal, delay means receiving in said first signal for delaying said first signal by a predetermined delay time period to output the delayed signal as a second signal during a normal operation mode, means responsive to said test signal for changing said delay time period in a test operating mode, and evaluation means for evaluating said operation performed by said second means.

Claim 34

A method as recited in claim 22, wherein the duration of said decreased nominal delay period is approximately one half the duration of said nominal time delay period.

Claim 35

A method as recited in claim 22, wherein said step of establishing a test mode includes the step of applying at least one abnormal signal to at least one terminal of said circuit.

Claim 36

A method as recited in claim 24, wherein said at least one abnormal signal comprises a voltage above the supply voltage of said circuit to a predetermined terminal of said circuit.

Claim 37

A method as recited in claim 24, wherein said at least one abnormal signal comprises an abnormal sequence of signals.