Test system for random access memory

Claim 2

A test system for a random access memory comprising: clock pulse width varying means for varying a pulse width of driving pulses for a random access memory; a first latch means connected to an address input circuit of said random access memory for receiving the output clock signal of said clock pulse width varying means and latching an address input signal at the leading edge of said output clock signal; a second latch means connected to a data output circuit of said random access memory for latching a data output signal; both said first and second latch means being supplied with the same clock signals from said clock pulse width varying means; and comparison means connected to a data output circuit of said random access memory for comparing the output of said random access memory with a predeter­mined expectation value corresponding to address access time of the random access memory; the output of said comparison means being latched by the trailing edge of said clock pulse in said second latch means.

Claim 3

A system according to claim 1, wherein said clock pulse width varying means comprises a variable delay circuit constituted by a ring oscillator circuit responsive to an input clock signal, the delay value of said variable delay circuit being controlled by delay value control signals.

Claim 4

A system according to claim 1 or 2, wherein said comparison means comprises: a first wired OR circuit connected to true output sides of transistors controlled by true output signals of said read only memory; a second wired OR circuit connected to inversion output sides of transistors controlled by inversion output signals of said read only memory; a first NOR gate (51) responsive to a predetermined expectation value signal for delivering the true output and the inversion output; a second NOR gate (52) responsive to the output of said first wired OR circuit and said true output of said first NOR gate; and a third NOR gate (53) responsive to the output of said second wired OR circuit and said inversion output of said first NOR gate; and said second latch means comprises: a fourth NOR gate (61) responsive to the output of said clock pulse width varying means for delivering the true output and the inversion output; said second NOR gate (52); said third NOR gate (53); a fifth NOR gate (62) responsive to the inversion output of said fourth NOR gate (61); and a sixth NOR gate (63) responsive to the outputs of said second (52), third (53), and fifth (62) NOR gates; the true output of said fourth NOR gate (61) being supplied to said second (52) and third (53) NOR gates, the output of said sixth NOR gate (63) being supplied to said fifth NOR gate (62).

Claim 5

A system according to claim 1, 2, or 3 wherein said clock pulse width varying means is incorporated in a RAM or an LSI tester.