Capacitively coupled read-only memory

Claim 2

A read-only memory for storing plural bits of information comprising: a plurality of memory cells arranged in an array, each said memory cell including capacitor means having a relatively high capacitance or a relatively low capacitance for representing a bit of information stored therein, wherein said capacitor means comprises a single capacitor for providing said relatively high capacitance or a pair of series coupled capacitors for providing said relatively low capacitance.

Claim 3

A read-only memory as defined in claim 1 wherein said read-only memory is formed on a substrated and wherein each said memory cell comprises a first insulating layer overlying said substrate, a first conductor overlying said first insulating layer, a second insulating layer overlying said first conductor, said second insulating layer being relatively thin, a conductive region overlying said second insulating layer, a third insulating layer overlying said conductive region, said third insulating layer being relatively thick, and a second conductor overlying said third insulating layer, wherein said capacitor means of relatively high capacitance includes a pore formed in said third insulating layer for permitting said second conductor to electrically contact said conductor region, whereby said first conductor, said second insulating layer and said conductive region provide said relatively high capacitance between said first and second conductors, and wherein said capacitor means of relatively low capacitance includes a first and second series coupled capacitors, said first capacitor including said first conductor, said second insulating layer, and said conductive region, and said second capacitor including said conductive region, said third insulating layer, and said second conductor, whereby said first and second series coupled capacitors provide said relatively low capacitance between said first and second conductors.

Claim 4

A read-only memory as defined in claim 2 wherein said memory cells are arranged in columns and rows, wherein said first conductor of each said cell of a given row of cells are coupled together to form a plurality of substantially parallel row conductors, and wherein said second conductor of each said cell of a given column of cells are coupled together to form a plurality of substantially parallel column conductors, said row conductors and said column conductors being substantially perpendicular to each other.

Claim 5

A read-only memory as defined in claim 3 wherein said row conductors are formed from a doped polycrystalline semiconductor material.

Claim 6

A read-only memory as defined in claim 4 wherein said semiconductor material is silicon.

Claim 7

A read-only memory as defined in claim 3 wherein said column conductors are formed from metal.

Claim 8

A read-only memory as defined in claim 3 wherein said conductive region of each said memory cell is formed from metal.

Claim 9

A read-only memory as defined in claim 3 wherein said insulating layers are formed from silicon oxide.

Claim 10

A read-only memory as defined in claim 3 further including a reference conductor substantially parallel to said row conductors and a plurality of reference capacitors, each said reference capacitor being coupled between said reference conductor and a respective given one of said column conductors.

Claim 11

A read-only memory as defined in claim 9 wherein each said reference capacitor has a capacitance on the order of one-half the capacitance of said relatively high capacitance.

Claim 12

A read-only memory as defined in claim 1 further including reading means for accessing each said memory cell one at a time and for providing a first output responsive to a memory cell having said relatively high capacitance and a second output responsive to a memory cell having said relatively low capacitance.

Claim 13

A read-only memory as defined in claim 11 wherein said first output is a low logic output and said second output is a high logic output.

Claim 14

A read-only memory as defined in claim 11 wherein said memory cells are arranged in columns and rows, wherein said read-only memory further comprises a plurality of substantially parallel row conductors, each said row conductor being coupled to one side of said capacitor means of the memory cells in a respective given one of said rows and a plurality of substantially parallel column conductors, each said column conductor being coupled to the other side of said capacitor means of the memory cells in a respective given one of said columns, and wherein said reading means comprises a sense amplifier coupled to each of said column conductors.

Claim 15

A read-only memory as defined in claim 13 further including a reference conductor extending substantially parallel to said row conductors and a plurality of reference capacitors, each said reference capacitor being coupled between said reference conductor and a respective given one of said column conductors.

Claim 16

A read-only memory for storing a plurality of bits of information, said read-only memory comprising: a plurality of memory cells arranged in an array of a plurality of substantially parallel rows and a plurality of substantially parallel columns, said rows being substantially perpendicular to said columns; a corresponding plurality of substantially parallel row conductors and substantially parallel column conductors, said row conductors being substantially perpendicular to said column conductors; each said memory cell including capacitor means coupled between a respective different pair of said row and column conductors, said capacitor means having a relatively high capacitance or a relatively low capacitance representing a bit of stored information; and reading means for accessing each said memory cell and providing a first or second output responsive to the capacitance level of said memory cell capacitance means, wherein said relatively high capacitance comprises a single capacitance coupled between a pair of said row and column conductors and wherein said relatively low capacitance comprises a pair of series coupled capacitances coupled between a pair of said row and column conductors.

Claim 17

A read-only memory for storing a plurality of bits of information, said read-only memory comprising: a plurality of memory cells arranged in an array of a plurality of substantially parallel rows and a plurality of substantially parallel columns, said rows being substantially perpendicular to said columns; a corresponding plurality of substantially parallel row conductors and substantially parallel column conductors, said row conductors being substantially perpendicular to said column conductors; each said memory cell including capacitor means coupled between a respective different pair of said row and column conductors, said capacitor means having a relatively high capacitance or a relatively low capacitance representing a bit of stored information; and reading means for accessing each said memory cell and providing a first or second output responsive to the capacitance level of said memory cell capacitance means, wherein said relatively high capacitance comprises a single capacitance coupled between a pair of said row and column conductors and wherein said relatively low capacitance comprises a pair of series coupled capacitances coupled between a pair of said row and column conductors.

Claim 18

A read-only memory as defined in claim 15 further including a reference conductor

Claim 19

A read-only memory as defined in claim 16 wherein said reading means comprises a sense amplifier coupled to each said column conductor.

Claim 20

A read-only memory as defined in claim 16 wherein said reference capacitors have a capacitance substantially equal to one-half said relatively high capacitance.

Claim 21

A read-only memory as defined in claim 15 wherein said high capacitance is on the order of ten times the capacitance of said relatively low capacitance.

Claim 22

A read-only memory as defined in claim 19 wherein said single capacitance has a given capacitance and said pair of series coupled capacitances comprise a first capacitance having said given capacitance and a second capacitance having one-tenth said given capacitance.