Patent US3503170A successfully refreshed from Google Patents.
Patent US5018168A successfully refreshed from Google Patents.
US5018168A
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Clock signal conversion circuit
Assignee: Fujitsu Ltd
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Filing: 1990-02-09
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Granted: 1991-05-21
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Expires: 2010-02-09
Abstract
Abstract A clock signal conversion circuit receives a clock signal and a control signal and generates a converted clock signal. A flip-flop holds the control signal in response to the clock signal and outputs a held control signal. The clock signal is selectively masked by an or gate in response to the held control signal thereby outputting the converted clock signal. A set signal is generated by a NAND gate in response to the clock signal, the control signal and the held control signal. The flip-flop forces the control signal to a predetermined state in response to the set signal generated by the NAND gate.
Inventors
- 👤 Takeru Matsuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:58
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/01; H03K5/04; H03K5/05
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
103 words
A clock signal conversion circuit which receives a clock signal and a control signal and generates a converted clock signal, said clock signal conversion circuit comprising: holding means for holding the control signal in response to the clock signal and outputting a held control signal; masking means for selectively masking the clock signal in response to the held control signal and outputting the converted clock signal; and generating means for generating a set signal in response to the clock signal, the control signal and the held control signal, said holding means being forced to a predetermined state in response to the set signal.
Claim 2
Dependent Claim
103 words
A clock signal conversion circuit which receives a clock signal and a control signal and generates a converted clock signal, said clock signal conversion circuit comprising: holding means for holding the control signal in response to the clock signal and outputting a held control signal; masking means for selectively masking the clock signal in response to the held control signal and outputting the converted clock signal; and generating means for generating a set signal in response to the clock signal, the control signal and the held control signal, said holding means being forced to a predetermined state in response to the set signal.
Claim 3
Dependent Claim
34 words
A clock signal conversion circuit according to claim 1, wherein said holding means comprises a D-type flip-flop operatively connected to said masking means and said generating means to receive the clock and control signals.
Claim 4
Dependent Claim
81 words
A clock signal conversion circuit according to claim 2, wherein said D-type flip-flop comprises a flip-flop circuit having a data input terminal for receiving the control signal, a clock input terminal for receiving the clock signal, an output terminal connected to said masking means for outputting the held control signal, an inverted output terminal operatively connected to said generating means for outputting an inverted held control signal, and a set terminal connected to said generating means for receiving the set signal.
Claim 5
Dependent Claim
50 words
A clock signal conversion circuit according to claim 3, wherein said generating means comprises a NAND gate operatively connected to said flip-flop circuit for receiving the clock signal, the control signal and the inverted held control signal and outputting the set signal to the set terminal of said flip-flop circuit.
Claim 6
Dependent Claim
38 words
A clock signal conversion circuit according to claim 1, wherein said masking means comprises an OR-gate operatively connected to said holding means for receiving the clock signal and the held control signal and outputting the converted clock signal.
Claim 7
Dependent Claim
21 words
A clock signal conversion circuit according to claim 1, wherein the clock signal has a period smaller than the control signal.
Claim 8
Dependent Claim
21 words
A clock signal conversion circuit according to claim 1, wherein the control signal is asynchronous with respect to the control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |