Reframe circuit in a synchronous multiplexing device

Claim 1

A reframe means in a synchronous multiplexing device comprising: a frame synchronizing pattern detection means for detecting whether a frame synchronizing pattern in a received data stream is the same as a predetermined synchronizing pattern, for providing the result thereof as a first output signal (X) and for providing a second output signal (FER) in an out-of-frame state; a frame pattern bit error detection means responsive to a serial data stream from the frame synchronizing pattern detection means, for comparing the serial data stream with a predetermined serial frame pattern, for detecting bit error in the data stream, for guarding whether the detected bit error exceeds an error threshold value (Eth) and for providing the result thereof as an output signal (BER); an in-frame/out-of-frame state discrimination means responsive to the output signal (BER) from the frame pattern bit error detection means and the second output signal (FER) in the out-of-frame state from the frame synchronizing pattern detection means, for discriminating in an in-frame state, as a normal in-frame state (I) if the error in a frame synchronizing signal train is less than or equal to the error threshold (Eth), for discriminating in an in-frame state, as a pre-alarm state (J) if the error exceeds the error threshold (Eth) and for discriminating in an in-frame state, as the out-of-frame state when the error exceeds the error threshold continuously more than a predetermined number of times, and for guarding in the out-of-frame state, whether a predetermined frame synchronizing signal train is detected at a position of the next frame signal expected from the detected frame synchronizing pattern, for being processed in a frame pattern search steps (B through H) determining whether the detected frame synchronizing pattern is produced accidentially, and then for providing the result as an output signal (W); a counter phase synchronizing means responsive to the output signal (W) from the in-frame/out-of-frame state discrimination means, the first output signal (X) from the frame synchronizing pattern detection means and a reference phase signal (Y), for providing as an output signal (Z) a parallel loading mode for fixing phase while operation in the in-frame state and a count-up mode for counting until the state becomes the in-frame state while operation in the out-of-frame state and; a counter and timing generation means responsive to an operating mode control signal (z) from the counter phase synchronizing means, for operating in the parallel loading mode or in the count-up mode, for generating a timing signal in accordance with each of the operating modes and then for supplying them to each means and a system classifying a received multiplexed data.