Patent US5016259A successfully refreshed from Google Patents.
US5016259A
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Low jitter DDFS FSK modulator
Assignee: Grass Valley Group Inc
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Filing: 1989-03-03
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Granted: 1991-05-14
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Expires: 2009-03-03
Abstract
Abstract A low jitter direct digital frequency synthesized frequency shift keyed modulator has a tapped delay line to provide polyphase sampling of an asynchronous data input signal. The samples from the tapped delay line are input to a correction signal generator that produces a correction signal as a function of the location of data transitions in the data input signal with respect to a specified point of a sample clock pulse. The correction signal is used to offset a modulating input to a direct digital frequency synthesizer so that the frequency shift keyed output reflects the data transitions within 1/n of the period of the sample clock pulse.
Inventors
- 👤 David L. Hershberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:50
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/12; H04L27/122
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
126 words
An apparatus for reducing jitter in the data transitions of an asynchronous data input where such data transitions occur at intervals NT, where N is an integer greater than zero, said apparatus comprising: means for generating a sample clock having a period t shorter than T, means for sampling the data input at intervals t/n, wherein is an integer greater than unity, to produce n samples of the data input during each sample clock period; means for generating a correction signal from the sampled data input as a function of the location of the data transitions within the sample clock period relative to one edge of the sample clock pulse; and means for offsetting a digital ramp signal representing the data transitions by the correction signal.
Claim 2
Independent Claim
126 words
An apparatus for reducing jitter in the data transitions of an asynchronous data input where such data transitions occur at intervals NT, where N is an integer greater than zero, said apparatus comprising: means for generating a sample clock having a period t shorter than T, means for sampling the data input at intervals t/n, wherein is an integer greater than unity, to produce n samples of the data input during each sample clock period; means for generating a correction signal from the sampled data input as a function of the location of the data transitions within the sample clock period relative to one edge of the sample clock pulse; and means for offsetting a digital ramp signal representing the data transitions by the correction signal.
Claim 3
Dependent Claim
60 words
An apparatus as recited in claim 1 wherein the sampling means comprises: a tapped delay line having taps located at delay time intervals equal to 1/n times the period of the sample clock pulse to provide n outputs; and means for sampling the n outputs at a specified time relative to the sample clock pulse to produce the n samples.
Claim 4
Dependent Claim
48 words
An apparatus as recited in claim 1 wherein the generating means comprises: means for determining from the n samples the location of the data transitions relative to one edge of the sample clock pulse; and means for generating the correction signal from the location of the data transitions.
Claim 5
Dependent Claim
37 words
An apparatus as recited in claim 1 wherein the offsetting means comprises: means for generating the digital ramp signal in response to the data transitions; and means for adding the correction signal to the digital ramp signal.
Claim 6
Dependent Claim
131 words
An improved direct digital frequency synthesized frequency shift keyed modulator of the type having a sine lookup table to output a digital sinusoid and a ramp generator to provide a modulating input that changes the constant value input when there are transitions in data input, the improvement comprising: means for polyphase sampling the data input to produce n samples for each sample clock pulse; means for generating a correction signal as a function of the data transitions as represented by the n samples; means for offsetting the modulating input by the correction signal so that the change to the constant value input is closer in time to the data transitions; and means for integrating said constant value input and feeding the result into the sine lookup table using a Euler integrator.
Claim 7
Dependent Claim
131 words
An improved direct digital frequency synthesized frequency shift keyed modulator of the type having a sine lookup table to output a digital sinusoid and a ramp generator to provide a modulating input that changes the constant value input when there are transitions in data input, the improvement comprising: means for polyphase sampling the data input to produce n samples for each sample clock pulse; means for generating a correction signal as a function of the data transitions as represented by the n samples; means for offsetting the modulating input by the correction signal so that the change to the constant value input is closer in time to the data transitions; and means for integrating said constant value input and feeding the result into the sine lookup table using a Euler integrator.
Claim 8
Dependent Claim
61 words
An improved direct digital frequency synthesized frequency shift keyed modulator as recited in claim 5 wherein the polyphase sampling means comprises: a tapped delay line having taps located at delay time intervals equal to 1/n times the period of the sample clock pulse to provide n outputs; and means for sampling the n outputs substantially simultaneously to produce the n samples.
Claim 9
Dependent Claim
56 words
An improved direct digital frequency synthesized frequency shift keyed modulator as recited in claim 5 wherein the generating means comprises: means for determining from the n samples the location of the data transitions relative to one edge of the sample clock pulse; and means for generating the correction signal from the location of the data transitions.
Claim 10
Dependent Claim
45 words
An improved direct digital frequency synthesized frequency shift keyed modulator as recited in claim 5 wherein the offsetting means comprises: means for generating a digital ramp signal in response to the data transitions; and means for adding the correction signal to the digital ramp signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-13 | 1994-11-12 | 1995-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-13 | 1998-11-12 | 1999-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-13 | 2002-11-12 | 2003-05-14 | $7700.00 | Window Closed / Lapsed |