Low sensitivity switched-capacitor ladder filter using monolithic MOS chip

Claim 2

A switched-capacitor filter for passing an input audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate comprising: a first amplifier having input and output terminals; a first integrator capacitor interconnected to said first amplifier; a second amplifier having input and output terminals; a second integrator capacitor interconnected to said second amplifier; a first input switched-capacitor interconnected between said input terminal of said first amplifier and said output terminal of said second amplifier, such that said first input switched-capacitor samples and holds the output of said second amplifier during a first clock phase thereby isolating said output terminal of said second amplifier from said first integrating capacitor and during a second clock phase applies the sampled and held output of said second amplifier to said first integrator capacitor; and a second input switched-capacitor interconnected between said output terminal of said first amplifier and said input terminal of said second amplifier, such that during said second clock phase said second input switched-capacitor applies the output of said first amplifier to said second integrator capacitor.

Claim 3

The switched-capacitor filter of claim 1 and further including switch means interconnected to said first amplifier and said first input switched-capacitor.

Claim 4

The switched-capacitor filter of claim 2 wherein said switch means includes first, second, third and fourth switch means each having first and second terminals and a control terminal such that: said first terminal of said first switch means is interconnected to a ground voltage potential, said second terminal of said first switch means is interconnected to said first terminal of said second switch means to form a first node, said second terminal of said second switch means is interconnected to said input terminal of said first amplifier; said control terminal of said first switch means is interconnected to receive a first clock signal during said first clock phase; said control terminal of said second switch means is interconnected to receive a second clock signal during said second clock phase; said first terminal of said third switch means is interconnected to a voltage potential, said second terminal of said third switch means is interconnected to said first terminal of said fourth switch means to form a second node and said second terminal of said fourth switch means is interconnected to said output terminal of said second amplifier; said control terminal of said third switch means is interconnected to receive said second clock signal; and said control terminal of said fourth switch means is interconnected to receive said first clock signal.

Claim 5

The switched-capacitor filter of claim 3 wherein said first input switched-capacitor is interconnected between said first and second nodes.

Claim 6

The switched-capacitor filter of claim 3 wherein said voltage potential is ground potential.

Claim 7

The switched-capacitor filter of claim 1 and further including switch means interconnected to said second amplifier and said second input switched-capacitor.

Claim 8

The switched-capacitor filter of claim 6 wherein said switch means includes first, second, third and fourth switch means each having first and second terminals and a control terminal such that: said first terminal of said first switch means is interconnected to a ground voltage potential, said second terminal of said first switch means is interconnected to said first terminal of said second switch means to form a first node, said second terminal of said second switch means is interconnected to said input terminal of said second amplifier; said control terminal of said first switch means is interconnected to receive a first clock signal during said first clock phase; said control terminal of said second switch means is interconnected to receive a second control signal during said second clock phase; said first terminal of said third switch means is interconnected to said output terminal of said first amplifier, said second terminal of said third switch means is interconnected to said first terminal of said fourth switch means to form a second node and said second terminal of said fourth switch means is interconnected to a voltage potential; said control terminal of said third switch means is interconnected to receive said second clock signal; and said control terminal of said fourth switch means is interconnected to receive said first clock signal.

Claim 9

The switched-capacitor filter of claim 7 wherein said voltage potential is ground potential.

Claim 10

The switched-capacitor filter of claim 1 wherein said capacitors comprise MOS switched-capacitors.

Claim 11

The switched-capacitor filter of claim 1 wherein said first amplifier, first integrator capacitor and first input switched-capacitor introduce a phase lag in the input audio frequency signal and said second amplifier, second integrator capacitor and second input switched-capacitor introduce a phase lead in the audio frequency signal, such that the resulting processed signal has no phase shift.

Claim 12

The switched-capacitor filter of claim 1 and further including: a coupling capacitor interconnected to said input terminal of at least one of said amplifiers to receive an input signal to be processed wherein the switched-capacitor filter operates as a high-pass filter.

Claim 13

In a pulse-code modulation telecommunications system including an audio signal generating device and a coding/decoding device wherein a high-pass and low-pass filter are disposed between the generating device and the coding/decoding device, a switched-capacitor filter comprising: a first amplifier having input and output terminals; a first integrator capacitor interconnected to said first amplifier; a second amplifier having input and output terminals; a second integrator capacitor interconnected to said second amplifier; a first input switched-capacitor interconnected between said input terminal of said first amplifier and said output terminal of said second amplifier, such that said first input switched-capacitor samples and holds the output of said second amplifier during a first clock phase thereby isolating said output terminal of said second amplifier from said input terminal of said first amplifier and during a second clock phase applies the sampled and held output of said second amplifier to said first integrator capacitor; and a second input switched-capacitor interconnected between said output terminal of said first amplifier and said input terminal of said second amplifier, such that during said second clock phase said second input switched-capacitor applies the output of said first amplifier to said second integrator capacitor.

Claim 14

In a pulse-code modulation telecommunications system including an audio signal generating device and a coding/decoding device wherein a high-pass and low-pass filter are disposed between the generating device and the coding/decoding device, a switched-capacitor filter comprising: a first amplifier having input and output terminals; a first integrator capacitor interconnected to said first amplifier; a second amplifier having input and output terminals; a second integrator capacitor interconnected to said second amplifier; a first input switched-capacitor interconnected between said input terminal of said first amplifier and said output terminal of said second amplifier, such that said first input switched-capacitor samples and holds the output of said second amplifier during a first clock phase thereby isolating said output terminal of said second amplifier from said input terminal of said first amplifier and during a second clock phase applies the sampled and held output of said second amplifier to said first integrator capacitor; and a second input switched-capacitor interconnected between said output terminal of said first amplifier and said input terminal of said second amplifier, such that during said second clock phase said second input switched-capacitor applies the output of said first amplifier to said second integrator capacitor.

Claim 15

A switched-capacitor filter for passing an input audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate comprising: first differential amplifier means having an inverting input terminal and an output terminal; a first integrator capacitor interconnected between said inverting input terminal and output terminal of said first differential amplifier means; second differential amplifier means having an inverting input terminal and an output terminal; a second integrator capacitor interconnected between said inverting input terminal and output terminal of said second differential amplifier means; a first input switched-capacitor; first switch means interconnected to said first differential amplifier means and said first input switched-capacitor; a second input switched-capacitor; second switch means interconnected to said second differential amplifier means and said second input switched-capacitor; clock means interconnected to said switch means for generating first and second clock signals; said first input switched-capacitor interconnected to said first switch means and between said inverting input terminal of said first differential amplifier means and said output of said second differential amplifier means, such that said first input switched-capacitor samples and holds the output of said second differential amplifier means when said switch means receives said first clock signal thereby isolating said output of said second differential amplifier means from said inverting input terminal of said first differential amplifier means and such that when said switch means receives said second clock signal the output of said second differential amplifier means is applied to said first integrator capacitor to introduce a phase lag in the input audio frequency; and said second input switched-capacitor interconnected to said second switch means and between said output terminal of said first differential amplifier means and said inverting input terminals of said second differential amplifier means, such that when said switch means receives said second clock signal said second input switched-capacitor applies the output of said first differential amplifier means to said second integrator capacitor to introduce a phase lead in the input audio frequency.

Claim 16

A switched-capacitor filter for passing an input audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate comprising: first differential amplifier means having an inverting input terminal and an output terminal; a first integrator capacitor interconnected between said inverting input terminal and output terminal of said first differential amplifier means; second differential amplifier means having an inverting input terminal and an output terminal; a second integrator capacitor interconnected between said inverting input terminal and output terminal of said second differential amplifier means; a first input switched-capacitor; first switch means interconnected to said first differential amplifier means and said first input switched-capacitor; a second input switched-capacitor; second switch means interconnected to said second differential amplifier means and said second input switched-capacitor; clock means interconnected to said switch means for generating first and second clock signals; said first input switched-capacitor interconnected to said first switch means and between said inverting input terminal of said first differential amplifier means and said output of said second differential amplifier means, such that said first input switched-capacitor samples and holds the output of said second differential amplifier means when said switch means receives said first clock signal thereby isolating said output of said second differential amplifier means from said inverting input terminal of said first differential amplifier means and such that when said switch means receives said second clock signal the output of said second differential amplifier means is applied to said first integrator capacitor to introduce a phase lag in the input audio frequency; and said second input switched-capacitor interconnected to said second switch means and between said output terminal of said first differential amplifier means and said inverting input terminals of said second differential amplifier means, such that when said switch means receives said second clock signal said second input switched-capacitor applies the output of said first differential amplifier means to said second integrator capacitor to introduce a phase lead in the input audio frequency.

Claim 17

A switched-capacitor filter for passing an input audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate comprising: first differential amplifier means having an inverting input terminal and an output terminal; a first integrator capacitor interconnected between said inverting input terminal and output terminal of said first differential amplifier means; second differential amplifier means having an inverting input terminal and an output terminal; a second integrator capacitor interconnected between said inverting input terminal and output terminal of said second differential amplifier means; a first input switched-capacitor; clock means for generating first and second clock signals during first and second clock phases; first switch means interconnected to said first differential amplifier means and said first input switched-capacitor; said first switch means including first, second, third and fourth switch means each having first and second terminals and a control terminal such that: said first terminal of said first switch means is interconnected to a ground voltage potential, said second terminal of said first switch means is interconnected to said first terminal of said second switch means to form a first node, said second terminal of said second switch means is interconnected to said inverting input terminal of said first differential amplifier means; said control terminal of said first switch means is interconnected to receive said first clock signal during said first clock phase; said control terminal of said second switch means is interconnected to receive said second clock signal during said second clock phase; said first terminal of said third switch means is interconnected to a voltage potential, said second terminal of said third switch means is interconnected to said first terminal of said fourth switch means to form a second node and said second terminal of said fourth switch means is interconnected to said output terminal of said second differential amplifier means; said control terminal of said third switch means is interconnected to receive said second clock signal during said second clock phase; and said control terminal of said fourth switch means is interconnected to receive said first clock signal during said first clock phase; a second input switched-capacitor; second switch means interconnected to said second differential amplifier means and said second input switched-capacitor; said second switch means including fifth, sixth, seventh and eighth switch means each having first and second terminals and a control terminal such that: said first terminal of said fifth switch means is interconnected to a ground voltage potential, said second terminal of said fifth switch means is interconnected to said first terminal of said sixth switch means to form a third node, said second terminal of said sixth switch means is interconnected to said input terminal of said second differential amplifier means; said control terminal of said fifth switch means is interconnected to receive said first clock signal during said first clock phase; said control terminal of said sixth switch means is interconnected to receive said second clock signal during said second clock phase; said first terminal of said seventh switch means is interconnected to said output terminal of said first differential amplifier means, said second terminal of said seventh switch means is interconnected to said first terminal of said eighth switch means to form a fourth node and said second terminal of said eighth switch means is interconnected to a voltage potential; said control terminal of said seventh switch means is interconnected to receive said second clock signal during said second clock phase; and said control terminal of said eighth switch means is interconnected to receive said first clock signal during said first clock phase; said first input switched-capacitor interconnected between said first and second nodes, such that said first input switched-capacitor samples and holds the output of said second differential amplifier means when said switch means receives said first clock signal thereby isolating said output of said second differential amplifier means from said inverting input terminal of said first differential amplifier means and such that when said switch means receives said second clock signal the sampled and held output of said second differential amplifier means is applied to said first integrator capacitor to introduce a phase lag in the input audio frequency; and said second input switched-capacitor interconnected between said third and fourth nodes, such that when said switch means receives said second clock signal said second input switched-capacitor applies the output of said first differential amplifier means to said second integrator capacitor to introduce a phase lead in the input audio frequency.

Claim 18

A switched-capacitor filter for passing an input audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate comprising: first differential amplifier means having an inverting input terminal and an output terminal; a first integrator capacitor interconnected between said inverting input terminal and output terminal of said first differential amplifier means; second differential amplifier means having an inverting input terminal and an output terminal; a second integrator capacitor interconnected between said inverting input terminal and output terminal of said second differential amplifier means; a first input switched-capacitor; clock means for generating first and second clock signals during first and second clock phases; first switch means interconnected to said first differential amplifier means and said first input switched-capacitor; said first switch means including first, second, third and fourth switch means each having first and second terminals and a control terminal such that: said first terminal of said first switch means is interconnected to a ground voltage potential, said second terminal of said first switch means is interconnected to said first terminal of said second switch means to form a first node, said second terminal of said second switch means is interconnected to said inverting input terminal of said first differential amplifier means; said control terminal of said first switch means is interconnected to receive said first clock signal during said first clock phase; said control terminal of said second switch means is interconnected to receive said second clock signal during said second clock phase; said first terminal of said third switch means is interconnected to a voltage potential, said second terminal of said third switch means is interconnected to said first terminal of said fourth switch means to form a second node and said second terminal of said fourth switch means is interconnected to said output terminal of said second differential amplifier means; said control terminal of said third switch means is interconnected to receive said second clock signal during said second clock phase; and said control terminal of said fourth switch means is interconnected to receive said first clock signal during said first clock phase; a second input switched-capacitor; second switch means interconnected to said second differential amplifier means and said second input switched-capacitor; said second switch means including fifth, sixth, seventh and eighth switch means each having first and second terminals and a control terminal such that: said first terminal of said fifth switch means is interconnected to a ground voltage potential, said second terminal of said fifth switch means is interconnected to said first terminal of said sixth switch means to form a third node, said second terminal of said sixth switch means is interconnected to said input terminal of said second differential amplifier means; said control terminal of said fifth switch means is interconnected to receive said first clock signal during said first clock phase; said control terminal of said sixth switch means is interconnected to receive said second clock signal during said second clock phase; said first terminal of said seventh switch means is interconnected to said output terminal of said first differential amplifier means, said second terminal of said seventh switch means is interconnected to said first terminal of said eighth switch means to form a fourth node and said second terminal of said eighth switch means is interconnected to a voltage potential; said control terminal of said seventh switch means is interconnected to receive said second clock signal during said second clock phase; and said control terminal of said eighth switch means is interconnected to receive said first clock signal during said first clock phase; said first input switched-capacitor interconnected between said first and second nodes, such that said first input switched-capacitor samples and holds the output of said second differential amplifier means when said switch means receives said first clock signal thereby isolating said output of said second differential amplifier means from said inverting input terminal of said first differential amplifier means and such that when said switch means receives said second clock signal the sampled and held output of said second differential amplifier means is applied to said first integrator capacitor to introduce a phase lag in the input audio frequency; and said second input switched-capacitor interconnected between said third and fourth nodes, such that when said switch means receives said second clock signal said second input switched-capacitor applies the output of said first differential amplifier means to said second integrator capacitor to introduce a phase lead in the input audio frequency.

Claim 19

A switched-capacitor filter comprising: a first amplifier having input and output terminals; a first integrator capacitor interconnected to said first amplifier; a second amplifier having input and output terminals; a second integrator capacitor interconnected to said second amplifier; a first input switched-capacitor interconnected between said input terminal of said first amplifier and said output terminal of said second amplifier, such that said first input switched-capacitor samples and holds the output of said second amplifier during a first clock phase thereby isolating said output terminal of said second amplifier from said first integrator capacitor and during a second clock phase applies the sampled and held output of said second amplifier to said first integrator capacitor; and a second input switched-capacitor interconnected between said output terminal of said first amplifier and said input terminal of said second amplifier, such that during said second clock phase said second input switched-capacitor applies the output of said first amplifier to said second integrator capacitor.

Claim 20

A switched-capacitor filter comprising: a first amplifier having input and output terminals; a first integrator capacitor interconnected to said first amplifier; a second amplifier having input and output terminals; a second integrator capacitor interconnected to said second amplifier; a first input switched-capacitor interconnected between said input terminal of said first amplifier and said output terminal of said second amplifier, such that said first input switched-capacitor samples and holds the output of said second amplifier during a first clock phase thereby isolating said output terminal of said second amplifier from said first integrator capacitor and during a second clock phase applies the sampled and held output of said second amplifier to said first integrator capacitor; and a second input switched-capacitor interconnected between said output terminal of said first amplifier and said input terminal of said second amplifier, such that during said second clock phase said second input switched-capacitor applies the output of said first amplifier to said second integrator capacitor.