US5014099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic RAM cell with trench capacitor and trench transistor
Assignee: Texas Instruments Inc
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Filing: 1990-03-08
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Granted: 1991-05-07
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Expires: 2010-03-08
Abstract
Abstract A dynamic random access memory cell has a storage capacitor and an access transistor formed on the sidewalls of a trench etched into the face of a silicon bar. The storage capacitor uses the sidewalls of the trench as the storage node, and uses a polysilicon plug as a common or grounded node. This polysilicon plug is part of a grounded field plate that surrounds the cell on the face and functions to provide isolation between cells. The channel of the access transistor is formed in a minor trench using the upper part of the sidewall of only one side of the major trench; an upper edge of the capacitor storage node functions as the source region of the transistor, while a buried N+ region on the face adjacent the trench is the drain. The gate of the transistor is a conductor extending along the face over the field plate except where it extends down into the minor trench at the channel area.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
255 words
A one-transistor dynamic random-access memory cell formed in the face of a monocrystalline semiconductor body of a first conductivity type comprising: a trench region having a bottom portion in the semiconductor body and a wall portion extending from the face into the semiconductor body to the bottom portion; a first capacitor region of a second conductivity type formed along the trench wall portion and extending from the bottom portion to a position along the wall portion and spaced from the face of the semiconductor body; a conductive plug filling most of the trench; a conductive layer formed over and in electrical contact with the conductive plug, said layer extending away from the trench region and positioned between the wordline and the face to provide a field plate over a portion of the face adjoining the trench region; a dielectric material providing electrical isolation between the capacitor region and the conductive plug; a first source/drain region of the second conductivity type formed in the semiconductor body on the face or on the wall portion, said first source/drain region separated from the first capacitor region by a channel region or the first conductivity type along the wall portion, a portion of the first capacitor region including a second source/drain region adjoining the channel region; a minor recess formed in the trench adjacent the channel region and extending from the face to the first capacitor region; and a wordline along the face and including a gate layer positioned in the recess to selectively render the channel region conductive.
Claim 2
Dependent Claim
255 words
A one-transistor dynamic random-access memory cell formed in the face of a monocrystalline semiconductor body of a first conductivity type comprising: a trench region having a bottom portion in the semiconductor body and a wall portion extending from the face into the semiconductor body to the bottom portion; a first capacitor region of a second conductivity type formed along the trench wall portion and extending from the bottom portion to a position along the wall portion and spaced from the face of the semiconductor body; a conductive plug filling most of the trench; a conductive layer formed over and in electrical contact with the conductive plug, said layer extending away from the trench region and positioned between the wordline and the face to provide a field plate over a portion of the face adjoining the trench region; a dielectric material providing electrical isolation between the capacitor region and the conductive plug; a first source/drain region of the second conductivity type formed in the semiconductor body on the face or on the wall portion, said first source/drain region separated from the first capacitor region by a channel region or the first conductivity type along the wall portion, a portion of the first capacitor region including a second source/drain region adjoining the channel region; a minor recess formed in the trench adjacent the channel region and extending from the face to the first capacitor region; and a wordline along the face and including a gate layer positioned in the recess to selectively render the channel region conductive.
Claim 3
Dependent Claim
20 words
The memory cell of claim 1 further including an insulative layer positioned between the channel region and the gate layer.
Claim 4
Dependent Claim
13 words
The memory cell of claim 1 wherein the first conductivity type is P-type.
Claim 5
Dependent Claim
14 words
The memory cell of claim 1 wherein the conductive plug is formed of polysilicon.
Claim 6
Dependent Claim
132 words
A memory comprising a plurality of memory cells formed in a semiconductor layer of a first conductivity type, each of said cells including a storage capacitor and an access transistor at least partially formed in a trench and each cell further comprising: a first capacitor region of a second conductivity type formed along the bottom portion of said trench wall and spaced from the face of said semiconductor layer; a conductive plug filling most of the trench; a conductive reference plate in electrical contact with said conductive plug and extending away from said trench region and over said semiconductor layer to provide a field plate adjacent said trench; a dielectric material providing electrical isolation between said capacitor region and said conductive plug; and a transistor formed along a sidewall of said trench.
Claim 7
Dependent Claim
132 words
A memory comprising a plurality of memory cells formed in a semiconductor layer of a first conductivity type, each of said cells including a storage capacitor and an access transistor at least partially formed in a trench and each cell further comprising: a first capacitor region of a second conductivity type formed along the bottom portion of said trench wall and spaced from the face of said semiconductor layer; a conductive plug filling most of the trench; a conductive reference plate in electrical contact with said conductive plug and extending away from said trench region and over said semiconductor layer to provide a field plate adjacent said trench; a dielectric material providing electrical isolation between said capacitor region and said conductive plug; and a transistor formed along a sidewall of said trench.
Claim 8
Dependent Claim
42 words
The memory of claim 5, wherein: said first capacitor region is formed as a doped region in the sidewalls of said trench, and a portion of said doped region further serves as a source/drain region of a corresponding one of said transistor.
Claim 9
Dependent Claim
36 words
The memory of claim 5, wherein: said transistor has a channel region in said sidewall and an insulated gate formed by a conductive layer over said semiconductor layer and extending into a portion of said trench.
Claim 10
Dependent Claim
25 words
The memory of claim 5, wherein: (a) said semiconductor layer is silicon; (b) said transistor is a MOSFETs; and (c) said reference plate is polysilicon.
Claim 11
Dependent Claim
31 words
The memory of claim 5, wherein: said reference plate is connected to a reference plate of another one of said cells to form a single layer with openings for said transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |