Patent US5013985A successfully refreshed from Google Patents.
US5013985A
Expired / Lapsed
US
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Microcomputer with motor controller circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1990-04-25
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Granted: 1991-05-07
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Expires: 2010-04-25
Abstract
Abstract A microcomputer with a motor controller circuit includes a motor controller circuit (4) which has NAND circuits (8) for producing a logical product of a rise pulse from a rise pulse generator (5) and a start level from a register (7) and flip-flop circuits (9a-9b) each responsive to start level set signals from the NAND circuits and an output pulse from a three-phase inverter waveform generator timer (6a-6b) to generate three-phase inverter waveforms.
Inventors
- 👤 Mitsuhiro Itoh
- 👤 Hideo Matsui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:21
CPC Classifications
H; H02; H02P; H02P23/00; H02P23/0077
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
139 words
A microcomputer with a motor controller circuit, which comprises: a microcomputer including a central processing unit, a memory, a timer, and a clock for generating clock pulses, said timer including: a rise pulse generator in response to said clock pulses to generate rise pulses; and three three-phase inverter waveform generation timers responsive to said rise pulses to generate output pulses; and a motor controller circuit incorporated in said microcomputer, said motor controller circuit including: a register in which said CPU sets start levels for said three-phase inverter waveform generation timers; three pairs of NAND circuits for producing a logical product of said rise pulse and said start level; and three flip-flop circuits responsive to start level set signals from said NAND circuits and an output pulse from said three-phase inverter waveform generation timer to generate a three-phase inverter waveform.
Claim 2
Dependent Claim
139 words
A microcomputer with a motor controller circuit, which comprises: a microcomputer including a central processing unit, a memory, a timer, and a clock for generating clock pulses, said timer including: a rise pulse generator in response to said clock pulses to generate rise pulses; and three three-phase inverter waveform generation timers responsive to said rise pulses to generate output pulses; and a motor controller circuit incorporated in said microcomputer, said motor controller circuit including: a register in which said CPU sets start levels for said three-phase inverter waveform generation timers; three pairs of NAND circuits for producing a logical product of said rise pulse and said start level; and three flip-flop circuits responsive to start level set signals from said NAND circuits and an output pulse from said three-phase inverter waveform generation timer to generate a three-phase inverter waveform.
Claim 3
Dependent Claim
34 words
The microcomputer with a motor controller circuit of claim 1, wherein said rise pulse generator is a synchronizing timer which is used in a timer mode to convert clock pulses to one-shot rise pulses.
Claim 4
Dependent Claim
25 words
The microcomputer with a motor controller circuit of claim 1, wherein said three-phase inverter waveform generation timers are used in a one-shot pulse output mode.
Claim 5
Dependent Claim
25 words
The microcomputer with a motor controller circuit of claim 1, wherein said three-phase inverter waveform generation timers are used in a pulse width modulation mode.
Claim 6
Dependent Claim
25 words
The microcomputer with a motor controller circuit of claim 1, wherein said three-phase inverter waveform generation timers are used in a continuous pulse output mode.
Claim 7
Dependent Claim
32 words
The microcomputer with a motor controller circuit of claim 1, wherein said rise pulse generator and said three-phase inverter waveform generation timers are assigned to part of said timer within said microcomputer.
Claim 8
Dependent Claim
60 words
The microcomputer with a motor controller circuit of claim 1, wherein said flip-flop circuits are clocked to be responsive to start level set signals inputted to S and R terminals from said NAND circuits and an output pulse inputted to a T terminal from said three-phase inverter waveform generation timer to output three-phase inverter waveforms at Q and Q terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |