US5013679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cell capacitor of a dynamic random access memory and a method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1989-09-05
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Granted: 1991-05-07
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Expires: 2009-09-05
Abstract
Abstract In a cell capacitor of a dynamic random access memory cell according to the present invention, an insulation film is formed on the surface of a fine trench formed in a silicon semiconductor substrate. A contact hole is formed in the insulation film in a region on the side wall of the trench. A polysilicon film is formed on the side wall of the trench in a hollow-cylindrical shape. A silicon layer is epitaxially and selectively grown on the polysilicon film and on the silicon substrate exposed through the contact hole. The polysilicon film and the silicon layer constitute an information storage electrode. At least the silicon layer of the information storage electrode is electrically connected to a source or a drain region of a transfer transistor of the memory cell. A gate insulation film is formed on the surface of the silicon layer. A counter electrode is formed such that the counter electrode is embedded in the trench.
Inventors
- 👤 Jumpei Kumagai
- 👤 Susumu Yoshikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/01
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
116 words
A method of manufacturing a cell capacitor of a dynamic random access memory, comprising the steps of: forming a trench in a semiconductor substrate; exposing a portion of said semiconductor substrate, which is located in a region on a side wall of said trench; forming a semiconductor layer on the side wall of said trench; causing an electrically conductive layer to be epitaxially and selectively grown only on said semiconductor layer and on the exposed portion of said semiconductor substrate, and integrating said electrically conductive layer during the growth; forming a gate insulation film on a surface of said electrically conductive layer; and forming a counter electrode on said gate insulation film and within said trench.
Claim 2
Independent Claim
116 words
A method of manufacturing a cell capacitor of a dynamic random access memory, comprising the steps of: forming a trench in a semiconductor substrate; exposing a portion of said semiconductor substrate, which is located in a region on a side wall of said trench; forming a semiconductor layer on the side wall of said trench; causing an electrically conductive layer to be epitaxially and selectively grown only on said semiconductor layer and on the exposed portion of said semiconductor substrate, and integrating said electrically conductive layer during the growth; forming a gate insulation film on a surface of said electrically conductive layer; and forming a counter electrode on said gate insulation film and within said trench.
Claim 3
Dependent Claim
14 words
The method according to claim 1, wherein said semiconductor layer has an electrical conductivity.
Claim 4
Dependent Claim
12 words
The method according to claim 1, wherein said trench includes a hole.
Claim 5
Dependent Claim
12 words
The method according to claim 1, wherein said trench includes a groove.
Claim 6
Dependent Claim
53 words
The method according to claim 1, wherein said region on the side wall of the trench includes a plurality of areas, and said electrically conductive layer is formed by epitaxial growth on said semiconductor substrate opening to said plurality of areas on the side wall of the trench, and on said semiconductor layer.
Claim 7
Dependent Claim
51 words
The method according to claim 1, wherein said region on the side wall of the trench includes a single area, and said electrically conductive layer is formed by epitaxial growth on said semiconductor substrate opening to said single area on the side wall of the trench, and on said semiconductor layer.
Claim 8
Independent Claim
134 words
A method of manufacturing a cell capacitor of a dynamic random access memory, comprising the steps of: forming a trench in a semiconductor substrate; forming an insulation film on an inner surface of said trench; forming a semiconductor layer on a side wall of said trench; exposing a portion of said semiconductor substrate, which is located in a region on an upper surface of the semiconductor substrate in the vicinity of said trench; causing an electrically conductive layer to be epitaxially and selectively grown only on said semiconductor layer and on the exposed portion of said semiconductor substrate, and integrating said electrically conductive layer during the growth; forming a gate insulation film on the surface of said electrically conductive layer; and forming a counter electrode on said gate insulation film and within said trench.
Claim 9
Independent Claim
134 words
A method of manufacturing a cell capacitor of a dynamic random access memory, comprising the steps of: forming a trench in a semiconductor substrate; forming an insulation film on an inner surface of said trench; forming a semiconductor layer on a side wall of said trench; exposing a portion of said semiconductor substrate, which is located in a region on an upper surface of the semiconductor substrate in the vicinity of said trench; causing an electrically conductive layer to be epitaxially and selectively grown only on said semiconductor layer and on the exposed portion of said semiconductor substrate, and integrating said electrically conductive layer during the growth; forming a gate insulation film on the surface of said electrically conductive layer; and forming a counter electrode on said gate insulation film and within said trench.
Claim 10
Dependent Claim
14 words
The method according to claim 7, wherein said semiconductor layer has an electrical conductivity.
Claim 11
Dependent Claim
12 words
The method according to claim 7, wherein said trench includes a hole.
Claim 12
Dependent Claim
12 words
The method according to claim 7, wherein said trench includes a groove.
Claim 13
Dependent Claim
77 words
The method according to claim 7, wherein said region on the upper surface of the semiconductor substrate in the vicinity of said trench includes the entire peripheral region of a verge of an opening of the trench, and said electrically conductive layer is formed by epitaxial growth on said entire peripheral region of the verge of the opening of the trench, which is located on the upper surface of the semiconductor substrate, and on said semiconductor layer.
Claim 14
Dependent Claim
81 words
The method according to claim 7, wherein said region on the upper surface of the semiconductor substrate in the vicinity of said trench includes a portion of the peripheral region of a verge of an opening of the trench, and said electrically conductive layer is formed by epitaxial growth on said portion of the peripheral region of the verge of the opening of the trench, which is located on the upper surface of the semiconductor substrate, and on said semiconductor layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |