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US5012472A
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Dynamic type semiconductor memory device having an error checking and correcting circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1988-12-22
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Granted: 1991-04-30
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Expires: 2008-12-22
Abstract
Abstract In a memory cell comprising a data cell array and a parity cell array, an error checkingxcorrecting circuit is connected to each of the arrays through a selector. The selector is constituted by transistors connected to each of the bit lines in the memory cell. The number of circuit elements constituting the error checkingxcorrecting circuit corresponds to one-half of the number of the bit line pairs included in the data cell array and the parity cell array. In an error correcting mode, half of the data appeared on the bit line pairs in data cell array and the parity cell array are transferred to the error checkingxcorrecting circuit by the selector, so that the errors are corrected. Thereafter, the data of the remaining half of the bit line pairs are processed in the same manner. Therefore, the number of circuit elements of the error checkingxcorrecting circuit can be reduced compared with the prior art, improving the degree of integration of the device.
Inventors
- 👤 Kazutami Arimoto
- 👤 Kiyohiro Furutani
- 👤 Koichiro Mashiko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
100 words
A semiconductor memory device having error correcting means incorporated in a memory cell array, comprising: a plurality of m bit line pair groups, each group having a plurality of n adjacent bit line pairs, wherein m and n are integers greater than 1; error correcting means having a plurality of m circuit elements for correcting any erroneous potential appearing on a bit line pair; and switching means for selectively connecting each of said plurality of n bit line pairs contained in each of said bit line pair groups to respective ones of said circuit elements of said error correcting means.
Claim 2
Dependent Claim
100 words
A semiconductor memory device having error correcting means incorporated in a memory cell array, comprising: a plurality of m bit line pair groups, each group having a plurality of n adjacent bit line pairs, wherein m and n are integers greater than 1; error correcting means having a plurality of m circuit elements for correcting any erroneous potential appearing on a bit line pair; and switching means for selectively connecting each of said plurality of n bit line pairs contained in each of said bit line pair groups to respective ones of said circuit elements of said error correcting means.
Claim 3
Dependent Claim
95 words
A semiconductor memory device according to claim 1, wherein said switching means comprises: a plurality of m times n select gates each connected to a respective one of each of said bit lines constituting all the bit line pairs contained in said bit line pair groups, each of said select gates being opened or closed in accordance with an applied signal; signal applying means for applying a signal to each of said select gates; and control-means for controlling the opening or closing of said select gates by changing the signal from said signal applying means.
Claim 4
Dependent Claim
24 words
A semiconductor memory device according to claim 2 having an error correcting mode, wherein said control means is activated in said error correcting mode.
Claim 5
Dependent Claim
19 words
A semiconductor memory device according to claim 3, wherein said error correcting mode is generated in a refresh cycle.
Claim 6
Dependent Claim
19 words
A semiconductor memory device according to claim 3, wherein said error correcting mode is generated in a reading cycle.
Claim 7
Dependent Claim
19 words
A semiconductor memory device according to claim 3, wherein said control means is also activated in a writing cycle.
Claim 8
Dependent Claim
113 words
A semiconductor memory device according to claim 1, wherein said error correcting means comprises: a syndrome generating circuit for generating a syndrome signal in accordance with a prescribed operation employing Hamming codes responsive to a signal supplied by one of the bit lines selected from each of said bit line pair groups connected to said syndrome generating circuit by said switching means; a syndrome decoder for decoding the syndrome signal generated by said syndrome generating circuit and, in response, generating a bit line error signal; and a data correcting circuit for inverting a potential of each of the bit lines constituting a bit line pair in response to said bit line error signal.
Claim 9
Dependent Claim
55 words
A semiconductor memory device according to claim 1, wherein said memory cell array comprises a data cell array and a parity cell array, and each of said bit line pair groups comprises at least one bit line pair in said data cell array and at least one bit line pair in said parity cell array.
Claim 10
Dependent Claim
92 words
A semiconductor memory device having error correcting means incorporated in a memory cell array, comprising: a plurality of m bit line pair groups each group having n adjacent bit line pair wherein m and n are integers greater than 1; error correcting means having m circuit elements for correcting an erroneous potential appearing on a bit line pair; and switching means for selectively connecting one bit line pair contained in each of said m bit line pair groups to a respective one of said n circuit elements of said error correcting means.
Claim 11
Dependent Claim
92 words
A semiconductor memory device having error correcting means incorporated in a memory cell array, comprising: a plurality of m bit line pair groups each group having n adjacent bit line pair wherein m and n are integers greater than 1; error correcting means having m circuit elements for correcting an erroneous potential appearing on a bit line pair; and switching means for selectively connecting one bit line pair contained in each of said m bit line pair groups to a respective one of said n circuit elements of said error correcting means.
Claim 12
Dependent Claim
10 words
A semiconductor memory device according to claim 9, wherein n=2.
Claim 13
Dependent Claim
77 words
A semiconductor memory device according to claim 10, wherein said switching means comprises: a plurality of select gates each connected to each of the bit lines constituting all the bit line pairs contained in said bit line pair groups, one half of the gates being opened and the remaining half of the gates being closed in accordance with types of signals applied thereto; and signal applying means for applying two signals to each of said select gates.
Claim 14
Dependent Claim
24 words
A semiconductor memory device according to claim 11 having an error correcting mode, wherein said switching means is activated in said error correcting mode.
Claim 15
Dependent Claim
19 words
A semiconductor memory device according to claim 12, wherein said error correcting mode is generated in a refresh cycle.
Claim 16
Dependent Claim
19 words
A semiconductor memory device according to claim 12, wherein said error correcting mode is generated in a reading cycle.
Claim 17
Dependent Claim
19 words
A semiconductor memory device according to claim 12, wherein said control means is activated also in a writing cycle.
Claim 18
Dependent Claim
96 words
A semiconductor memory device according to claim 9, wherein said error correcting comprises: a syndrome generating circuit for generating a syndrome signal in accordance with a prescribed operation employing Hamming codes, based on the potential of each of the bit lines of at least one bit line pair connected thereto; a syndrome decoder for decoding the syndrome signal generated by said syndrome generating circuit; and a data correcting circuit for inverting the potential of each of the bit lines constituting the bit line pair on which an error is generated, based on said decoded syndrome signal.
Claim 19
Dependent Claim
23 words
A semiconductor memory device according to claim 9, wherein said memory cell array comprises a data cell array and a parity cell array.
Claim 20
Dependent Claim
151 words
A semiconductor memory device having error correcting means incorporated in a memory cell array formed on a common semiconductor substrate, comprising: a plurality of m bit line pair groups each having n adjacent bit line pairs formed on said semiconductor substrate, wherein m and n are integers greater than 1; error correcting means formed on said semiconductor substrate at a common end of said m bit line pair groups, said error correcting means having m circuit elements for correcting an erroneous potential appearing on a bit line pair, a pitch of said m circuit elements on said substrate being equal to a pitch of said m bit line pair groups; and switching means for selectively connecting one bit line pair of said n adjacent bit line pairs contained in each of said m bit line pair groups to a respective one of said n circuit elements of said error correcting means.
Claim 21
Dependent Claim
151 words
A semiconductor memory device having error correcting means incorporated in a memory cell array formed on a common semiconductor substrate, comprising: a plurality of m bit line pair groups each having n adjacent bit line pairs formed on said semiconductor substrate, wherein m and n are integers greater than 1; error correcting means formed on said semiconductor substrate at a common end of said m bit line pair groups, said error correcting means having m circuit elements for correcting an erroneous potential appearing on a bit line pair, a pitch of said m circuit elements on said substrate being equal to a pitch of said m bit line pair groups; and switching means for selectively connecting one bit line pair of said n adjacent bit line pairs contained in each of said m bit line pair groups to a respective one of said n circuit elements of said error correcting means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |