Digital PLL circuit having reduced lead-in time

Claim 1

A digital PLL circuit for outputting a clock signal phase-synchronized with an input signal comprising: a fixed frequency generator generating an output signal having a frequency which is n-times as large as a frequency f 0 of the clock signal, a delay circuit generating a plurality of signals formed by giving predetermined and various phase differences to the output signal of said fixed frequency generator, a phase changing circuit successively selecting one of said plurality of signals depending on a control input to output the selected signal, a divider dividing a frequency of the output signal of said phase changing circuit by n to output said clock signal, a phase comparator comparing a phase of said clock signal with a phase of said input signal, and a phase control pulse generator outputting a control signal to said phase changing circuit depending on a result of comparison of said phase comparator, characterized in that said divider being able to be set to a predetermined state in which said divider raises said clock signal, and that the digital PLL circuit further comprises a signal initiation pulse generator generating a signal to set said divider to said predetermined state depending on said input signal initiation.