US4841167A
Expired / Lapsed
US
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Clock recovering device
Assignee: NEC Corp
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Filing: 1987-08-27
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Granted: 1989-06-20
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Expires: 2007-08-27
Abstract
Abstract A device for recovering a clock from received data which has a different duty ratio is disclosed. The optimum timing of a recovered clock is determined based on the pulse width of received data. A clock is accurately recovered so long as the duty ratio of received data is not greater than ±50%.
Inventors
- 👤 Noboru Saegusa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:28
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
142 words
A clock recovering device comprising: an edge detector means for producing a pulse when received data changes; a first counter means for counting a high-speed clock which is an integral multiple times higher than a transmission rate of the received data, and reset by the pulse output of said edge detector means; a logic means for processing an output of said first counter means; a second counter means for receiving an output of said logic means and reset by the pulse output for counting the high-speed clock; a phase comparator means for deciding a phase of recovered clock by comparing the recovered clock with a carry which is output by said second counter means; and a variable frequency divider means controlled in frequency division number by an output of said phase comparator means for producing the recovered clock from the high-speed clock.
Claim 2
Dependent Claim
142 words
A clock recovering device comprising: an edge detector means for producing a pulse when received data changes; a first counter means for counting a high-speed clock which is an integral multiple times higher than a transmission rate of the received data, and reset by the pulse output of said edge detector means; a logic means for processing an output of said first counter means; a second counter means for receiving an output of said logic means and reset by the pulse output for counting the high-speed clock; a phase comparator means for deciding a phase of recovered clock by comparing the recovered clock with a carry which is output by said second counter means; and a variable frequency divider means controlled in frequency division number by an output of said phase comparator means for producing the recovered clock from the high-speed clock.
Claim 3
Dependent Claim
44 words
A clock recovering device as claimed in claim 1, wherein said first counter means comprises a first n-bit binary counter for counting a high-speed clock which is 2 n times higher than the transmission rate of the received data, and reset by the pulse.
Claim 4
Dependent Claim
28 words
A clock recovering device as claimed in claim 2, wherein said logic means comprises an inverter for inverting an "n-1" bit output of said first n-bit binary counter.
Claim 5
Dependent Claim
75 words
A clock recovering device as claimed in claim 3, wherein said second counter means comprises a second n-bit binary counter having an "n-1" bit input to which an output of said inverter is connected and an "n-2" to a "0" bit input to which an "n-1" to a "1" bit output of said first n-bit binary counter are respectively connected, so as to read data in response to the pulse, and counting the high-speed clock.
Claim 6
Dependent Claim
43 words
A clock recovering device as claimed in claim 1, wherein said first counter means comprises a first modulo N counter for counting a high-speed clock which is N times higher than the transmission rate of the received data, and reset by the pulse.
Claim 7
Dependent Claim
34 words
A clock recovering device as claimed in claim 5, wherein said logic means comprises a decoder for computing L=0.5N+0.5M (M<0.5N) and L=0.5M (M>0.5N) by using a count M of said first modulo N counter.
Claim 8
Dependent Claim
35 words
A clock recovering device as claimed in claim 6, wherein said second counter means comprises a second modulo N counter for counting the high-speed clock and set to an initial value L by the pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |