US4849703A
Expired / Lapsed
US
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Method and apparatus for generating a data sampling clock locked to a baud clock contained in a data signal
Assignee: Telogy Networks Inc
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Filing: 1988-04-01
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Granted: 1989-07-18
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Expires: 2008-04-01
Abstract
Abstract An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.
Inventors
- 👤 Matthew F. Easley
- 👤 German E. Correa
- 👤 Randy D. Nash
- 👤 Cynthia A. Panella
- 👤 Taruna Tjahjadi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:41
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0334; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04L27/00; H04L27/02; H04L27/08; H04L27/18; H04L27/20; H04L27/2032; H04L27/2053; H04L27/206; H04L27/2067; H04L27/2071; H04L27/32; H04L27/34; H04L27/36; H04L27/362; H04L9/00; H04L9/40; H04L7/0331
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
136 words
A method for synchronizing a data sampling clock to a baud clock contained in a data signal, said data sampling clock having a nominal frequency of N times a frequency of said baud clock, comprising the steps of: (a) sampling said data signal at said frequency of said data sampling clock to provide a sampled data signal; (b) squaring said sampled data signal to provide a squared sampled data signal; (c) filtering said squared sampled data signal to provide a recovered baud clock; (d) determining a sign of said recovered baud clock on every Nth occurrence of said data sampling clock; and (e) increasing said frequency of said data sampling clock if said sign is of a predetermined polarity, and decreasing said frequency of said data sampling clock if said sign is of a reverse polarity.
Claim 2
Independent Claim
136 words
A method for synchronizing a data sampling clock to a baud clock contained in a data signal, said data sampling clock having a nominal frequency of N times a frequency of said baud clock, comprising the steps of: (a) sampling said data signal at said frequency of said data sampling clock to provide a sampled data signal; (b) squaring said sampled data signal to provide a squared sampled data signal; (c) filtering said squared sampled data signal to provide a recovered baud clock; (d) determining a sign of said recovered baud clock on every Nth occurrence of said data sampling clock; and (e) increasing said frequency of said data sampling clock if said sign is of a predetermined polarity, and decreasing said frequency of said data sampling clock if said sign is of a reverse polarity.
Claim 3
Dependent Claim
9 words
The method of claim 1 wherein N equals 12.
Claim 4
Dependent Claim
19 words
The method of claim 1 wherein said frequency of said baud clock is 600 Hz and N equals 12.
Claim 5
Dependent Claim
13 words
The method or claim 1 wherein said predetermined polarity is a positive polarity.
Claim 6
Dependent Claim
24 words
The method of claim 1 wherein said filtering is bandpass filtering using a center frequency approximately equal to said frequency of said baud clock.
Claim 7
Dependent Claim
15 words
The method of claim 5 wherein said frequency of said baud clock is 600 Hz.
Claim 8
Independent Claim
258 words
A method for synchronizing a data sampling clock to a baud clock contained in a data signal, said data sampling clock having a nominal frequency of N times a frequency of said baud clock, comprising the steps of: (a) a start-up procedure, comprising: (1) sampling said data signal to provide a sampled data signal, said sampled data signal comprising a plurality of data signal sample points; (2) squaring said sampled data signal to provide a squared sample data signal; (3) filtering said squared sampled data signal to provide a recovered baud clock signal; (4) detecting a predetermined transition of said recovered baud clock signal; and (5) designating a sample point of said plurality of sample points nearest in time to said predetermined transistion as a primary sampling point; and (b) a maintenance procedure performed after completion of steps (a) (5) (1) sampling said data signal to provide said sampled data signal, said sampled data signal comprising a plurality of data signal sample points; (2) squaring said sampled data signal to provide said squared sampled data signal; (3) filtering said squared sampled data signal to provide said recovered baud clock signal; (4) determining a sign of said recovered baud clock on each Nth occurrence of said data sampling clock, beginning with said occurrence of said data sampling clock corresponding to said primary sampling point; and (5) increasing said frequency of said data sampling clock if said sign is of a predetermined polarity and decreasing said frequency of said data sampling clock if said sign is of a reverse polarity.
Claim 9
Independent Claim
258 words
A method for synchronizing a data sampling clock to a baud clock contained in a data signal, said data sampling clock having a nominal frequency of N times a frequency of said baud clock, comprising the steps of: (a) a start-up procedure, comprising: (1) sampling said data signal to provide a sampled data signal, said sampled data signal comprising a plurality of data signal sample points; (2) squaring said sampled data signal to provide a squared sample data signal; (3) filtering said squared sampled data signal to provide a recovered baud clock signal; (4) detecting a predetermined transition of said recovered baud clock signal; and (5) designating a sample point of said plurality of sample points nearest in time to said predetermined transistion as a primary sampling point; and (b) a maintenance procedure performed after completion of steps (a) (5) (1) sampling said data signal to provide said sampled data signal, said sampled data signal comprising a plurality of data signal sample points; (2) squaring said sampled data signal to provide said squared sampled data signal; (3) filtering said squared sampled data signal to provide said recovered baud clock signal; (4) determining a sign of said recovered baud clock on each Nth occurrence of said data sampling clock, beginning with said occurrence of said data sampling clock corresponding to said primary sampling point; and (5) increasing said frequency of said data sampling clock if said sign is of a predetermined polarity and decreasing said frequency of said data sampling clock if said sign is of a reverse polarity.
Claim 10
Dependent Claim
9 words
The method of claim 7 wherein N equals 12.
Claim 11
Dependent Claim
19 words
The method of claim 7 wherein said frequency of said baud clock is 600 Hz and N equals 12.
Claim 12
Dependent Claim
13 words
The method of claim 7 wherein said predetermined polarity is a positive polarity.
Claim 13
Dependent Claim
22 words
The method of claim 7 wherein said filtering is bandpass filtering center frequency approximately equal to said frequency of said baud clock.
Claim 14
Dependent Claim
15 words
The method of claim 11 wherein said frequency of said baud clock is 600 Hz.
Claim 15
Dependent Claim
177 words
Apparatus for synchronizing a data sampling clock to a baud clock having a frequency and contained in an input signal, comprising: a clock; programmable counter means responsive to said clock and to a count control signal for providing said data sampling clock, said data sampling clock having a nominal frequency of N times said frequency of said baud clock; sampling means responsive to said data sampling clock for sampling said input signal to provide a sampled input signal; squaring means connected to said sampling means for providing a squared input signal; filtering means connected to said squaring means for providing a recovered baud clock signal; and calculating means responsive to said data sampling clock and to a sign of said recovered baud clock signal for updating said count control signal on every Nth occurrence of said data sampling clock; wherein said frequency of said data sampling clock is increased if said sign is of a first polarity on a said Nth occurrence and decreased if said sign is of a reverse polarity on a said Nth occurrence.
Claim 16
Dependent Claim
177 words
Apparatus for synchronizing a data sampling clock to a baud clock having a frequency and contained in an input signal, comprising: a clock; programmable counter means responsive to said clock and to a count control signal for providing said data sampling clock, said data sampling clock having a nominal frequency of N times said frequency of said baud clock; sampling means responsive to said data sampling clock for sampling said input signal to provide a sampled input signal; squaring means connected to said sampling means for providing a squared input signal; filtering means connected to said squaring means for providing a recovered baud clock signal; and calculating means responsive to said data sampling clock and to a sign of said recovered baud clock signal for updating said count control signal on every Nth occurrence of said data sampling clock; wherein said frequency of said data sampling clock is increased if said sign is of a first polarity on a said Nth occurrence and decreased if said sign is of a reverse polarity on a said Nth occurrence.
Claim 17
Dependent Claim
14 words
The apparatus of claim 13 wherein said programmable counter means comprises a presettable counter.
Claim 18
Dependent Claim
13 words
The apparatus of claim 13 wherein said filtering means comprises a bandpass filter.
Claim 19
Dependent Claim
20 words
The apparatus of claim 15 wherein said bandpass filter has a center frequency approximately equal to said baud clock frequency.
Claim 20
Dependent Claim
9 words
The apparatus of claim 13 wherein N equals 12.
Claim 21
Dependent Claim
11 words
The apparatus of claim 13 wherein said predetermined polarity is positive.
Claim 22
Dependent Claim
13 words
The apparatus of claim 13 wherein said samping means comprises a coder/decoder receiver.
Claim 23
Dependent Claim
21 words
The apparatus of claim 13 wherein said squaring means, said filtering means, and said calculating means are embodied in a microprocessor.
Claim 24
Dependent Claim
101 words
The apparatus of claim 13 and further comprising: zero-crossing detection means responsive to a predetermined transition said recovered baud clock signal for providing a zero-crossing signal; wherein said sampled input signal comprises a plurality of sampling points; and wherein said calculating means first designates a sampling point of said plurality of sampling points nearest in time to said predetermined transition as a primary sampling point and is then responsive to said sign for updating said control signal on every Nth occurrence of said data sampling clock beginning with said occurrence of said data sampling clock corresponding to said primary sampling point.
Claim 25
Dependent Claim
25 words
The apparatus of claim 21 wherein said squaring means, said filtering means, said calculating means, and said zero-crossing detection means are embodied in a microprocessor.
Claim 26
Dependent Claim
216 words
In a modem having means for sending outgoing signals over a telephone line and means for receiving incoming signals over said telephone line, said outgoing signals and said incoming signals corresponding to data being transferred at a rate determined by a baud clock having a frequency, said receiving means including means responsive to a sampling signal for sampling said incoming signals to produce a sampled signal, a sampling signal synchronization circuit for synchronizing said sampling signal to said baud clock in said incoming signals, comprising: a clock; programmable counter means responsive said clock and to a count control signal for providing said sampling signal, said sampling signal having a nominal frequency of N times said frequency of said baud clock; squaring means connected to said sampling means for providing a squared input signal; filtering means connected to said squaring means for providing a recovered baud clock signal; and calculating means responsive to said sampling signal and to a sign of said recovered baud clock signal for updating said count control signal on every Nth occurrence of said sampling signal; wherein said frequency of said sampling signal is increased if said sign is of a first polarity on a said Nth occurrence, and decreased if said sign is of a reverse polarity on a said Nth occurrence.
Claim 27
Dependent Claim
216 words
In a modem having means for sending outgoing signals over a telephone line and means for receiving incoming signals over said telephone line, said outgoing signals and said incoming signals corresponding to data being transferred at a rate determined by a baud clock having a frequency, said receiving means including means responsive to a sampling signal for sampling said incoming signals to produce a sampled signal, a sampling signal synchronization circuit for synchronizing said sampling signal to said baud clock in said incoming signals, comprising: a clock; programmable counter means responsive said clock and to a count control signal for providing said sampling signal, said sampling signal having a nominal frequency of N times said frequency of said baud clock; squaring means connected to said sampling means for providing a squared input signal; filtering means connected to said squaring means for providing a recovered baud clock signal; and calculating means responsive to said sampling signal and to a sign of said recovered baud clock signal for updating said count control signal on every Nth occurrence of said sampling signal; wherein said frequency of said sampling signal is increased if said sign is of a first polarity on a said Nth occurrence, and decreased if said sign is of a reverse polarity on a said Nth occurrence.
Claim 28
Dependent Claim
14 words
The circuit of claim 23 wherein said programmable counter means comprises a presettable counter.
Claim 29
Dependent Claim
14 words
The circuit of claim 24 wherein said filtering means comprises a band pass filter.
Claim 30
Dependent Claim
20 words
The circuit of claim 25 wherein said bandpass filter has a center frequency nominally equal to said baud clock frequency.
Claim 31
Dependent Claim
9 words
The circuit of claim 23 wherein N equals 12.
Claim 32
Dependent Claim
11 words
The circuit of claim 23 wherein said predetermined polarity is positive.
Claim 33
Dependent Claim
21 words
The circuit of claim 23 wherein said squaring means, said filtering means and said calculating means are embodied in a microprocessor.
Claim 34
Dependent Claim
99 words
The circuit of claim 23 and further comprising: zero-crossing detection means responsive to a predetermined transition of said recovered baud clock signal for providing a zero-crossing signal; wherein said sampled signal comprises a plurality of sampling points; and wherein said calculating means first designates a sampling point of said plurality of sampling points nearest in time to said predetermined transition as a primary sampling point and is then responsive to said sign for updating said control signal on every Nth occurrence of said sampling signal beginning with said occurrence of said sampling signal corresponding to said primary sampling point.
Claim 35
Dependent Claim
25 words
The circuit of claim 30 wherein said squaring means, said filtering means, said calculating means, and said zero-crossing detection means are embodied in a microprocessor.
References Cited (Backward Citations)
US4280099A
Cited
US4455661A
Cited
US4400817A
Cited
US4538119A
Cited
US4472818A
Cited
US4488294A
Cited
US4570125A
Cited
WO1985000255A1
Cited
US4620294A
Cited
EP0142302A2
Cited
EP0171856A1
Cited
JPS60167551A
Cited
US4680780A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |