US5012180A — System for testing internal nodes

Claim 1

Independent Claim 273 words

In an integrated circuit device having internal data and address buses respectively connectable to external data and address buses, and having normally accessible internal nodes addressable by normal addresses from the external address bus, the improvement comprising a test mode means (100, 111, 121) in the integrated circuit device for enabling external access of predetermined and normally inaccessible internal test nodes in the integrated circuit device, said test mode means comprising: a test mode decode means (103) responsive to an address from the external address bus for outputting a control signal to set the integrated circuit device in either a normal state or a test mode state, the normal state resulting from the address being one of the normal addresses and the test mode state resulting from the address being a predetermined address for initiating a test mode; a test mode control register means (105) for storing an address of a predetermined internal test node, said address being obtainable from the external data bus; a multiplexer means (101) responsive to the control signal for connecting the internal address bus (102) to the external address bus for receiving the normal addresses when in the normal state, and connecting to the test mode control register means for receiving the address of a predetermined internal test node when in the test mode state; and test node decoder means (111, 121) responsive to the control signal and the address of the predetermined internal test node for enabling the transfer of test data from the predetermined internal test node to the internal data bus, thereby allowing the normally inaccessible test node to be accessible from outside the device.

Claim 2

Dependent Claim 273 words

In an integrated circuit device having internal data and address buses respectively connectable to external data and address buses, and having normally accessible internal nodes addressable by normal addresses from the external address bus, the improvement comprising a test mode means (100, 111, 121) in the integrated circuit device for enabling external access of predetermined and normally inaccessible internal test nodes in the integrated circuit device, said test mode means comprising: a test mode decode means (103) responsive to an address from the external address bus for outputting a control signal to set the integrated circuit device in either a normal state or a test mode state, the normal state resulting from the address being one of the normal addresses and the test mode state resulting from the address being a predetermined address for initiating a test mode; a test mode control register means (105) for storing an address of a predetermined internal test node, said address being obtainable from the external data bus; a multiplexer means (101) responsive to the control signal for connecting the internal address bus (102) to the external address bus for receiving the normal addresses when in the normal state, and connecting to the test mode control register means for receiving the address of a predetermined internal test node when in the test mode state; and test node decoder means (111, 121) responsive to the control signal and the address of the predetermined internal test node for enabling the transfer of test data from the predetermined internal test node to the internal data bus, thereby allowing the normally inaccessible test node to be accessible from outside the device.

Claim 3

Dependent Claim 47 words

The test mode means of claim 1, further comprising an encoder which receives DMA access and channel select signals from an external control bus, said encoder generating a signal for inhibiting the test mode even when the control signal corresponds to that of the test mode state.

Claim 4

Dependent Claim 36 words

The test mode means of claim 1, wherein said test node decoder means includes at least one test write decoder for enabling the writing of data from the internal data bus into the selected internal nodes.

Claim 5

Dependent Claim 36 words

The test mode means of claim 1, wherein said test node decoder means includes at least one test read decoder for enabling the reading of data from the selected internal nodes onto the internal data bus.

Claim 6

Dependent Claim 18 words

The test mode means of claim 1, wherein said predetermined internal test node is that of a FIFO.

Claim 7

Dependent Claim 21 words

The test mode means of claim 1, wherein said predetermined internal test node is that of a cyclic redundancy check generator.

Claim 8

Dependent Claim 20 words

The test mode means of claim 1, wherein said predetermined internal test node is that of a clock signals multiplexer.

Claim 9

Dependent Claim 183 words

A test mode means included in an integrated circuit device for testing internal nodes in the integrated circuit device, said integrated circuit device being in communication with a microprocessor through an internal address bus, an external address bus and a data bus, and having device memory connected to the internal bus for storing data, said test mode means comprising: storage means for storing an address of a selected internal test node in the device, said internal test node being other than that of the device memory, and said address of the selected internal test node being obtainable from the external data bus; means responsive to a test command for selecting the address of the selected internal test node stored in the storage means and for supplying said address of the selected internal test node to the internal address bus; and test node decoder means responsive only to the address of the selected internal test node on the internal address bus for enabling the transfer of data between the selected internal test node and the data bus for testing the selected internal test node.

Claim 10

Dependent Claim 183 words

A test mode means included in an integrated circuit device for testing internal nodes in the integrated circuit device, said integrated circuit device being in communication with a microprocessor through an internal address bus, an external address bus and a data bus, and having device memory connected to the internal bus for storing data, said test mode means comprising: storage means for storing an address of a selected internal test node in the device, said internal test node being other than that of the device memory, and said address of the selected internal test node being obtainable from the external data bus; means responsive to a test command for selecting the address of the selected internal test node stored in the storage means and for supplying said address of the selected internal test node to the internal address bus; and test node decoder means responsive only to the address of the selected internal test node on the internal address bus for enabling the transfer of data between the selected internal test node and the data bus for testing the selected internal test node.

Claim 11

Dependent Claim 92 words

The test mode means of claim 8, wherein said selecting means includes: a test mode decode means for changing the value of a test mode in responsive to the test command; and a multiplexer means for connecting the internal address bus either to an external bus or to the storage means, said multiplexer connecting the internal address bus to the storage means when the test mode signal is of a first value and connecting the internal address bus to the external bus when the test mode signal is of a second value.

Claim 12

Dependent Claim 45 words

The test mode means of claim 9, further comprising an encoder which receives DMA access and channel select signals from an external control bus, said encoder generating a signal for inhibiting the test mode even when the test mode signal is of the first value.

Claim 13

Dependent Claim 34 words

The test mode means of claim 8, wherein said test node decoder means includes at least one test write decoder for enabling the writing of data from the bus into the selected internal nodes.

Claim 14

Dependent Claim 35 words

The test mode means of claim 8, wherein said test node decoder means includes at least one test read decoder for enabling the reading of data from the selected internal nodes onto the data bus.

Claim 15

Dependent Claim 18 words

The test mode means of claim 8, wherein said selected internal test node is that of a FIFO.

Claim 16

Dependent Claim 21 words

The test mode means of claim 8, wherein said selected internal test node is that of a cyclic redundancy check generator.

Claim 17

Dependent Claim 20 words

The test mode means of claim 8, wherein said selected internal test node is that of a clock signals multiplexer.

Claim 18

Dependent Claim 87 words

The test mode means of claim 8, wherein said selecting means includes: a test mode decode means for generating a select signal in response to the test command; and a multiplexer means for connecting the internal address bus either to an external bus or to the storage means, said multiplexer connecting the internal address bus to the storage means when the select signal is of a first value and connecting the internal address bus to the external bus when the select signal is of a second value.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-04-29	1994-10-29	1995-04-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-04-29	1998-10-29	1999-04-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-04-29	2002-10-29	2003-04-30	$7700.00	Window Closed / Lapsed

System for testing internal nodes

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