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US5010386A Expired / Lapsed US ⏱️ 0.0 years remaining

Insulator separated vertical CMOS

Assignee: Texas Instruments Inc
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Filing: 1989-12-26
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Granted: 1991-04-23
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Expires: 2009-12-26
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Abstract

Abstract A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of the first channel layer and an insulating layer is formed on the surface of the first source/drain layer. A second source/drain layer of the second conductivity type is formed on the surface of the insulating layer and a second channel layer of said first conductivity is formed on the surface of the second source/drain layer. A third source/drain layer of the second conductivity type is formed on the surface of the second channel layer. Gate circuitry is vertically disposed on an edge perpendicular to the plane and adjacent to the first and second channel layers and insulated therefrom.

Inventors

  • 👤 Robert Groover, III

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 22:57
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/837

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 137 words
A complementary semiconductor device structure comprising: a substrate of a first conductivity type; a first channel layer of a second conductivity type formed on the surface of said substrate; a first source/drain layer of said first conductivity type formed on the surface of said first channel layer; an insulating layer formed on the surface of said first source/drain layer; a second source/drain layer of said second conductivity type formed on the surface of said insulating layer; a second channel layer of said first conductivity type formed on the surface of said second source/drain layer; a third source/drain layer of said second conductivity type formed on the surface of said second channel layer; and gate circuitry vertically disposed on an edge perpendicular to the plane of and adjacent to said first and second channel layers, and insulated therefrom.
Claim 2
Dependent Claim 137 words
A complementary semiconductor device structure comprising: a substrate of a first conductivity type; a first channel layer of a second conductivity type formed on the surface of said substrate; a first source/drain layer of said first conductivity type formed on the surface of said first channel layer; an insulating layer formed on the surface of said first source/drain layer; a second source/drain layer of said second conductivity type formed on the surface of said insulating layer; a second channel layer of said first conductivity type formed on the surface of said second source/drain layer; a third source/drain layer of said second conductivity type formed on the surface of said second channel layer; and gate circuitry vertically disposed on an edge perpendicular to the plane of and adjacent to said first and second channel layers, and insulated therefrom.
Claim 3
Dependent Claim 25 words
The semiconductor structure of claim 1 and further comprising a conductive region connected to said first source/drain layer and insulated from said second source/drain layer.
Claim 4
Dependent Claim 25 words
The semiconductor structure of claim 1 and further comprising a conductive region connected to said second source/drain layer and insulated from said first source/drain layer.
Claim 5
Dependent Claim 20 words
The semiconductor structure of claim 1 and further comprising a conductive region connected to said first and second source/drain layers.
Claim 6
Dependent Claim 51 words
The semiconductor structure of claim 1 wherein said gate circuitry comprises: a first gate region defining a channel in said first conducting layer between said substrate and said first source/drain layer; and a second gate regions defining a channel in said second conducting layer between said second and third source/drain layers.
Claim 7
Dependent Claim 26 words
The semiconductor structure of claim 5 wherein said first conductivity type comprises P type conductivity and said second conductivity type comprises an N type conductivity type.
Claim 8
Dependent Claim 21 words
The semiconductor structure of claim 1 wherein said source/drain and channel layers are laterally isolated to define a hexagonal semiconductor mesa.
Claim 9
Dependent Claim 83 words
A semiconductor device comprising: a substrate; monocrystalline semiconductor mesas at the surface of the substrate; a first thin film conductive layer disposed below the surface of said mesas at a first predetermined depth to provide an electrical connection to predetermined ones of said mesas; and a second thin film conductive layer disposed below the surface of said mesas at a second predetermined depth to provide an electrical connection to predetermined ones of said mesas, said second contact electrically insulated from said first contact.
Claim 10
Dependent Claim 83 words
A semiconductor device comprising: a substrate; monocrystalline semiconductor mesas at the surface of the substrate; a first thin film conductive layer disposed below the surface of said mesas at a first predetermined depth to provide an electrical connection to predetermined ones of said mesas; and a second thin film conductive layer disposed below the surface of said mesas at a second predetermined depth to provide an electrical connection to predetermined ones of said mesas, said second contact electrically insulated from said first contact.
Claim 11
Dependent Claim 20 words
The semiconductor device of claim 8 wherein said mesa comprises first and second vertical transistors separated by an insulating layer.
Claim 12
Dependent Claim 34 words
The semiconductor device of claim 9 wherein said first contact is coupled to a source/drain of said first vertical transistor and said second source/drain is connected to a source/drain of said second vertical transistor.
Claim 13
Dependent Claim 15 words
The semiconductor device of claim 9 wherein said first vertical transistor comprises an N-channel transistor.
Claim 14
Dependent Claim 15 words
The semiconductor device of claim 11 wherein said second vertical transistor comprises a P-channel transistor.
Claim 15
Dependent Claim 16 words
The semiconductor device of claim 12 wherein said N-channel transistor is disposed above said P-channel transistor.
Claim 16
Dependent Claim 13 words
The semiconductor device of claim 8 wherein said mesa comprises a hexagonal-shaped mesa.
Claim 17
Dependent Claim 15 words
The semiconductor device of claim 14 wherein said first and second contacts comprise hexagonal-shaped contacts.
Claim 18
Dependent Claim 22 words
The semiconductor structure of claim 1, wherein said complimentary semiconductor device structure is connected in a circuit other than a CMOS inventor.

References Cited (Backward Citations)

US4450466A Cited
US4740826A Cited
US4810906A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-04-22 1994-10-22 1995-04-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-04-22 1998-10-22 1999-04-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-04-22 2002-10-22 2003-04-23 $7700.00 Window Closed / Lapsed

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