Semiconductor integrated circuit device having an improved arrangement of power source lines

Claim 2

A semiconductor integrated circuit device comprising: a plurality of functional blocks each executing respective logic operations and arranged in an internal area on a semiconductor chip; a first power source line arranged so as to surround said internal area and said plurality of functional blocks, said first power source line being a closed-loop line; second power source lines provided for each functional block of said plurality of functional blocks so as to surround each functional block on said chip, each of said second power source lines being a closed-loop line; and third power source lines mutually connecting said second power source lines of said functional blocks and connecting said second power source lines and said first power source line, said third power source lines connecting said second power source lines with other second power source lines and said second power source lines with said first power source line at a plurality of portions on said first and second power source lines.

Claim 3

A semiconductor integrated circuit device as claimed in claim 1, wherein each of said functional blocks includes a plurality of arrays each including unit cells each forming a logic unit, and wherein said semiconductor integrated circuit device further comprises a plurality of fourth power source lines which extend in the direction perpendicular to the direction of each of said arrays and are connected between opposite portions of related one of said second power source lines so that said unit cells are supplied with power through said fourth power source lines.

Claim 4

A semiconductor integrated circuit device as claimed in claim 2, further comprising a plurality of fifth power source lines which extend in the same direction as each of said arrays and are connected between opposite portions of related one of said second power source lines so that said unit cells are supplied with power through not only said fourth power source lines but also fifth power source lines.

Claim 5

A semiconductor integrated circuit device as claimed in claim 3, wherein said fifth power source lines include power source lines arranged between adjacent arrays among said plurality of arrays.

Claim 6

A semiconductor integrated circuit device as claimed in claim 4, wherein at least two power source lines included in said fourth power source lines are arranged between the adjacent arrays of unit cells.

Claim 7

A semiconductor integrated circuit device as claimed in claim 3, wherein said fifth power source lines include power source lines extending above said arrays.

Claim 8

A semiconductor integrated circuit device as claimed in claim 3, wherein said fourth and fifth power source lines are formed at different layer levels, and are in contact with each other through via holes.

Claim 9

A semiconductor integrated circuit device as claimed in claim 1, wherein said second power source lines include a duplex portion made up of a first line and a second line extending in parallel with each other.

Claim 10

A semiconductor integrated circuit device as claimed in claim 1, further comprising a sixth power source line arranged so as to surround said internal area and extend along said first power source line, and said sixth power source line is connected to said first and second power source lines through said third power source lines.

Claim 11

A semiconductor integrated circuit device as claimed in claim 1, wherein said functional blocks are classified into a plurality of groups, and said semiconductor integrated circuit device further comprises a seventh power source line arranged so as to surround each of said groups of functional blocks, and wherein said seventh power source lines provided for each said group of functional blocks are connected to said first and second power source lines by said third power source lines.

Claim 12

A semiconductor integrated circuit device as claimed in claim 1, further comprising an eighth power source line arranged so as to surround each of said plurality of functional blocks and extend along with one of said second power source lines, wherein said eighth power source lines provided for said functional blocks are connected to said first and second power source lines by said third power source lines.

Claim 13

A semiconductor integrated circuit device as claimed in claim 1, wherein said first power source line is wider than said second power source lines.

Claim 14

A semiconductor integrated circuit device as claimed in claim 1, wherein said second power source lines are wider than said third power source lines.

Claim 15

A semiconductor integrated circuit device as claimed in claim 1, wherein said first, second and third power source lines are of the same potential.

Claim 16

A semiconductor integrated circuit device comprising: a plurality of functional blocks each executing respective logic operations and arranged in an internal area on a semiconductor chip; a first high-potential power source line arranged so as to surround said internal area and said plurality of functional blocks, said high-potential first power source line being a closed-loop line; second high-potential power source lines provided for each functional block of said plurality of functional blocks so as to surround each functional block on said chip, each of said second high-potential power source lines being a closed-loop line; third high-potential power source lines mutually connecting said second high-potential power source lines of said functional blocks and connecting said second high-potential power source lines and said first high-potential power source line, said third high-potential power source lines connecting said second high-potential power source lines with other second high-potential power source lines and said second high-potential power source lines with said first high-potential power source line at a plurality of first portions on said first and second high-potential power source lines; a first low-potential power source line arranged so as to surround said internal area and said plurality of functional blocks, said first low-potential power source line being a closed-loop line; second low-potential power source lines provided for each functional block of said plurality of functional blocks so as to surround each functional block on said chip, each of said second low-potential power source lines being a closed-loop line; and third low-potential power source lines mutually connecting said second low-potential power source lines of said functional blocks and connecting said low-potential second power source lines and said first low-potential power source line, said third low-potential power source lines connecting said second low-potential power source lines with other second high-potential power source lines and said second low-potential power source lines with said first high-potential power source line at a plurality of second portions on said first and second low-potential power source.

Claim 17

A semiconductor integrated circuit device comprising: a plurality of functional blocks each executing respective logic operations and arranged in an internal area on a semiconductor chip; a first high-potential power source line arranged so as to surround said internal area and said plurality of functional blocks, said high-potential first power source line being a closed-loop line; second high-potential power source lines provided for each functional block of said plurality of functional blocks so as to surround each functional block on said chip, each of said second high-potential power source lines being a closed-loop line; third high-potential power source lines mutually connecting said second high-potential power source lines of said functional blocks and connecting said second high-potential power source lines and said first high-potential power source line, said third high-potential power source lines connecting said second high-potential power source lines with other second high-potential power source lines and said second high-potential power source lines with said first high-potential power source line at a plurality of first portions on said first and second high-potential power source lines; a first low-potential power source line arranged so as to surround said internal area and said plurality of functional blocks, said first low-potential power source line being a closed-loop line; second low-potential power source lines provided for each functional block of said plurality of functional blocks so as to surround each functional block on said chip, each of said second low-potential power source lines being a closed-loop line; and third low-potential power source lines mutually connecting said second low-potential power source lines of said functional blocks and connecting said low-potential second power source lines and said first low-potential power source line, said third low-potential power source lines connecting said second low-potential power source lines with other second high-potential power source lines and said second low-potential power source lines with said first high-potential power source line at a plurality of second portions on said first and second low-potential power source.

Claim 18

A semiconductor integrated circuit device as claimed in claim 15, wherein each of said functional blocks includes a plurality of arrays each including unit cells each forming a logic unit, and wherein said semiconductor integrated circuit device further comprises a plurality of fourth high-potential power source lines which extend in the direction perpendicular to the direction of each of said arrays and are connected between opposite portions of related one of said second high-potential power source lines, and a plurality of fourth low-potential power source lines which extend in the direction perpendicular to the direction of each of said arrays and are connected between opposite portions of related one of said second low-potential power source lines.

Claim 19

A semiconductor integrated circuit device as claimed in claim 16 further comprising a plurality of fifth high-potential power source lines which extend in the same direction as each of said arrays and connected between opposite portions of related one of said second high-potential power source lines, and a plurality of fifth low-potential power source lines which extend in the same direction as each of said arrays and are connected between opposite portions of related one of said second high-potential power source lines.

Claim 20

A semiconductor integrated circuit device as claimed in claim 17, wherein said fifth high-potential power source lines include power source lines arranged between adjacent arrays among said plurality of arrays, and said fifth low-potential power source lines include power source lines arranged between adjacent arrays among said plurality of arrays.

Claim 21

A semiconductor integrated circuit device as claimed in claim 16, wherein said fifth high-potential power source lines include power source lines extending above said arrays, and said fifth low-potential power source lines include power source lines extending above said arrays.