Voltage supply switching device for nonvolatile memories in MOS technology

Claim 1

A voltage supply switching device for nonvolatile memories in CMOS technology comprising two selection transistors inserted in respective circuit connection branches between two external pins with voltage Vcc and Vpp respectively and an internal node and a switching circuit controlling said selection transistors, wherein said selection transistors are the P channel type and there are provided circuit means to hold the body bias of said selection transistors at a voltage equal to the highest voltage from time to time present at said external pins; said device further comprising an analog comparator to compare to said voltages Vcc and Vpp and generate an output signal at two voltage levels depending upon the result of said comparison; said circuit means comprising at least one pair of P channel bias switching transistors inserted in respective connecting circuit branches between terminals with voltage Vpp and Vcc at a bias terminal for production of the bias voltage (Vb, Vbb) and means sensitive to the voltage level of the output signal of the comparator which control said bias switching transistors in such a manner as to transfer to said bias terminal the voltage, Vpp or Vcc, which said output signal indicates to be higher than the other.