US4833343A
Expired / Lapsed
US
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Clock generator having complementary transistors
Assignee: Siemens AG
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Filing: 1988-06-03
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Granted: 1989-05-23
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Expires: 2008-06-03
Abstract
Abstract A generator circuit in an integrated semiconductor circuit for generating a clock voltage having a voltage being raised with respect to a supply potential of the generator circuit includes a first CMOS inverter having an input connected to a first clock signal and having an output carrying a clock voltage as an output signal of the generator circuit. A second CMOS inverter has an input connected to a second clock signal and has an output. The inverters have transistors of a first conduction type with source terminals. A transfer transistor of the first conduction type is connected between the source terminals and a supply potential. A capacitor is connected between the source terminals and a pump signal. The transfer transistor has a gate terminal connected to the output of the second CMOS inverter.
Inventors
- 👤 Hans P. Fuchs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:37
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C8/00; G11C8/18; H03K17/00; H03K17/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
132 words
Generator circuit in an integrated semiconductor circuit for generating a clock voltage having a voltage being raised with respect to a supply potential of the generator circuit, comprising: a first CMOS inverter having an input connected to a first clock signal and having an output carrying a clock voltage as an output signal of the generator circuit; a second CMOS inverter having an input connected to a second clock signal and having an output; said inverters each having transistors of a first conduction type with source terminals, a transfer transistor of the first conduction type connected between said source terminals and a supply potential, and a capacitor connected between said source terminals and a pump signal; said transfer transistor having a gate terminal connected to said output of the second CMOS inverter.
Claim 2
Dependent Claim
132 words
Generator circuit in an integrated semiconductor circuit for generating a clock voltage having a voltage being raised with respect to a supply potential of the generator circuit, comprising: a first CMOS inverter having an input connected to a first clock signal and having an output carrying a clock voltage as an output signal of the generator circuit; a second CMOS inverter having an input connected to a second clock signal and having an output; said inverters each having transistors of a first conduction type with source terminals, a transfer transistor of the first conduction type connected between said source terminals and a supply potential, and a capacitor connected between said source terminals and a pump signal; said transfer transistor having a gate terminal connected to said output of the second CMOS inverter.
Claim 3
Dependent Claim
26 words
Generator circuit according to claim 1, wherein each of said transistors of the first conduction type have a substrate region connected to said source terminal thereof.
Claim 4
Dependent Claim
38 words
Generator circuit according to claim 1, wherein each of said transistors of the first conduction type have substrate regions connected to a trough voltage being at least as high as the maximum potential occurring in the generator circuit.
Claim 5
Dependent Claim
34 words
Generator circuit according to claim 1, wherein said inverters also have other transistors of a second conduction type opposite to said first conduction type, said other transistors having interconnected substrate regions and source terminals.
Claim 6
Dependent Claim
37 words
Generator circuit according to claim 1, wherein said inverters also have other transistors of a second conduction type opposite to said first conduction type, said other transistors having substrate regions connected to a separate substrate bias voltage.
Claim 7
Dependent Claim
61 words
Generator circuit according to claim 1, wherein said inverters also have other transistors of a second conduction type opposite to said first conduction type, said transistors of said second conduction type each having a substrate with a trough of said first conduction type therein, and each of said transistors of said first conduction type having substrate regions disposed in said trough.
Claim 8
Dependent Claim
51 words
Generator circuit according to claim 1, wherein said transistors of said first conduction type each have a substrate with a trough of a second conduction type opposite said first conduction type therein, and said inverters also have other transistors of said second conduction type having substrate regions disposed in said trough.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |