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US5003371A
Expired / Lapsed
US
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Fuse-melting device
Assignee: STMicroelectronics SA
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Filing: 1988-10-28
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Granted: 1991-03-26
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Expires: 2008-10-28
Abstract
Abstract The melting of a fuse of a CMOS type integrated circuit is caused by using the existence of a stray thyristor created in the neighborhood of the boundaries of pads made in a substrate. This stray thyristor is triggered by artificially making the potential drop in an intermediate region of the pad. The thyristor always comes on suddenly, the current that flows through the thyristor is very high and the phenomenon stops spontaneously when the fuse is melted.
Inventors
- 👤 Francois Tailliet
- 👤 Jacek Kowalski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:17
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
238 words
A device for the melting of a fuse in a CMOS type integrated circuit comprising a thyristor, series-mounted with the fuse, and means to control the turning on of this thyristor, wherein the thyristor comprises a semiconductor substrate with a first type of conductivity, said substrate being the substrate of the integrated circuit, a circular semiconducting pad of a second type of conductivity made in this substrate, a first region in the middle of the pad doped with impurities corresponding to the second type of conductivity and surrounded by a second circular region doped with impurities corresponding to the first type of conductivity, and on the inside rim of the pad, said circular pad being surrounded by a third circular region outside and in the neighborhood of the pad doped with impurities corresponding to the second type of conductivity, itself surrounded by a fourth circular region doped with impurities corresponding to the first type of impurities, the first and second doped region both being connected to a terminal of the fuse, the third and fourth doped region both being connected to a biasing potential of the substrate, the control means comprising a MOS type transistor formed by the alignment of a pad region, a substrate region and a third doped region outside the pad, a control gate of which being superimposed on a zone geographically in between the pad region and the third doped region outside the pad.
Claim 2
Independent Claim
238 words
A device for the melting of a fuse in a CMOS type integrated circuit comprising a thyristor, series-mounted with the fuse, and means to control the turning on of this thyristor, wherein the thyristor comprises a semiconductor substrate with a first type of conductivity, said substrate being the substrate of the integrated circuit, a circular semiconducting pad of a second type of conductivity made in this substrate, a first region in the middle of the pad doped with impurities corresponding to the second type of conductivity and surrounded by a second circular region doped with impurities corresponding to the first type of conductivity, and on the inside rim of the pad, said circular pad being surrounded by a third circular region outside and in the neighborhood of the pad doped with impurities corresponding to the second type of conductivity, itself surrounded by a fourth circular region doped with impurities corresponding to the first type of impurities, the first and second doped region both being connected to a terminal of the fuse, the third and fourth doped region both being connected to a biasing potential of the substrate, the control means comprising a MOS type transistor formed by the alignment of a pad region, a substrate region and a third doped region outside the pad, a control gate of which being superimposed on a zone geographically in between the pad region and the third doped region outside the pad.
Claim 3
Dependent Claim
18 words
A device according to claim 1, wherein the thyristor is a stray type thyristor of this integrated circuit.
Claim 4
Dependent Claim
81 words
A device according to either claim 1 or claim 2, comprising a circuit to enforce the potential of one terminal of the fuse after the melting of this fuse, this circuit being provided with a pull-back transistor, said pull-back transistor comprising two regions of a first type conductivity, made in a semiconductor material of opposite type conductivity, and only one of said regions being made in a vaster field of the same type conductivity, but with a lower concentration of impurities.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |