Patent US5001829A successfully refreshed from Google Patents.
US5001829A
Expired / Lapsed
US
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Method for connecting a leadless chip carrier to a substrate
Assignee: Lockheed Martin Corp
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Filing: 1990-01-02
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Granted: 1991-03-26
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Expires: 2010-01-02
Abstract
Abstract A Leadless Chip Carrier (LCC) is mounted on a circuit board on elongated solder posts to provide clearance between the LCC and the board. The process for producing solder posts involves the deposition of a temporary stencil surrounding the conductive pads on the board. The removable stencil around the pads provides support for molten solder during reflow and prevents the chip carrier from compressing the molten solder thereby insuring desirable spacing between the chip carrier and the board.
Inventors
- 👤 Robert L. Schelhorn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:48
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/3452; H05K3/341; H05K3/3431; H05K3/3442; H05K3/3465; H05K3/3485; H05K2201/00; H05K2201/09; H05K2201/09818; H05K2201/09909; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10727; H05K2203/00; H05K2203/05; H05K2203/0562; H05K2203/0568; H05K2203/07; H05K2203/0756; H05K2203/0769; H05K2203/0779; H05K2203/0783; H05K2203/0786; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
143 words
A method for connecting a leadless chip carrier having an array of peripheral metallic pads to a substrate having a corresponding array of metallic pads, including the steps of: covering said substrate with an optically sensitive material; treating said optically sensitive material with radiant energy to harden said optically sensitive material in selected areas other than those over said substrate pads; removing unhardened material to form a stencil, which defines chambers over said substrate pads; depositing solder paste in said chambers; positioning a chip carrier on said stencil with the peripheral pads aligned with the substrate pads and the solder paste in the chambers over the substrate pads; applying thermal energy to said chip carrier and substrate to melt the solder paste and form a solder joint between substrate pads and peripheral pads; and dissolving said stencil after said solder joint is formed.
Claim 2
Independent Claim
143 words
A method for connecting a leadless chip carrier having an array of peripheral metallic pads to a substrate having a corresponding array of metallic pads, including the steps of: covering said substrate with an optically sensitive material; treating said optically sensitive material with radiant energy to harden said optically sensitive material in selected areas other than those over said substrate pads; removing unhardened material to form a stencil, which defines chambers over said substrate pads; depositing solder paste in said chambers; positioning a chip carrier on said stencil with the peripheral pads aligned with the substrate pads and the solder paste in the chambers over the substrate pads; applying thermal energy to said chip carrier and substrate to melt the solder paste and form a solder joint between substrate pads and peripheral pads; and dissolving said stencil after said solder joint is formed.
Claim 3
Dependent Claim
25 words
A method according to claim 1, wherein said selected areas include an annular region surrounding a region centered within said array of peripheral metallic pads.
Claim 4
Independent Claim
162 words
A method for connecting a leadless chip carrier having an array of peripheral metallic pads to a substrate having a corresponding array of metallic pads, including the steps of: covering said substrate with a photoresist stencil material; exposing said photoresist to light through a negative of the substrate including said pad array, thereby hardening said photoresist stencil material in all areas exposed to light; removing unhardened portions of said photoresist stencil material from said substrate to form a stencil having a plurality of chambers over each of said substrate pads for receiving solder paste; depositing solder paste in said chambers; positioning a chip carrier on said stencil with the peripheral pads aligned with the substrate pads and the solder paste in the chambers over the substrate pads; applying thermal energy to said chip carrier and substrate to melt the solder paste and form a solder joint between substrate pads and peripheral pads; and dissolving said stencil after said solder joint is formed.
Claim 5
Independent Claim
162 words
A method for connecting a leadless chip carrier having an array of peripheral metallic pads to a substrate having a corresponding array of metallic pads, including the steps of: covering said substrate with a photoresist stencil material; exposing said photoresist to light through a negative of the substrate including said pad array, thereby hardening said photoresist stencil material in all areas exposed to light; removing unhardened portions of said photoresist stencil material from said substrate to form a stencil having a plurality of chambers over each of said substrate pads for receiving solder paste; depositing solder paste in said chambers; positioning a chip carrier on said stencil with the peripheral pads aligned with the substrate pads and the solder paste in the chambers over the substrate pads; applying thermal energy to said chip carrier and substrate to melt the solder paste and form a solder joint between substrate pads and peripheral pads; and dissolving said stencil after said solder joint is formed.
Claim 6
Independent Claim
134 words
A method for connecting a leadless chip carrier having an array of peripheral metallic pads to a substrate having a corresponding array of metallic pads, comprising the steps of: depositing a removable stencil around each of the pads on said substrate to form chambers over each of the substrate pads; depositing solder paste in said chamber through a mesh having an array of openings aligned with said array of peripheral metallic pads; positioning a chip carrier on said stencil with the peripheral pads aligned with the substrate pads and the solder paste in the chambers over the substrate pads; applying thermal energy to said chip carrier and substrate to melt the solder paste and form a solder joint between substrate pads and peripheral pads; and dissolving said stencil after said solder joint is formed.
Claim 7
Independent Claim
134 words
A method for connecting a leadless chip carrier having an array of peripheral metallic pads to a substrate having a corresponding array of metallic pads, comprising the steps of: depositing a removable stencil around each of the pads on said substrate to form chambers over each of the substrate pads; depositing solder paste in said chamber through a mesh having an array of openings aligned with said array of peripheral metallic pads; positioning a chip carrier on said stencil with the peripheral pads aligned with the substrate pads and the solder paste in the chambers over the substrate pads; applying thermal energy to said chip carrier and substrate to melt the solder paste and form a solder joint between substrate pads and peripheral pads; and dissolving said stencil after said solder joint is formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-25 | 1994-09-24 | 1995-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-25 | 1998-09-24 | 1999-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-25 | 2002-09-24 | 2003-03-26 | $7700.00 | Window Closed / Lapsed |