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US4763407A
Expired / Lapsed
US
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Method of manufacturing a semiconductor device
Assignee: Toshiba Corp
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Filing: 1987-05-21
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Granted: 1988-08-16
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Expires: 2007-05-21
Abstract
Abstract A semiconductor device mounted on a printed circuit board is disclosed. The semiconductor device is surrounded by a frame having a stopper portion on the inner wall thereof at a level higher than tops of bonding wires as well as a semiconductor element housed in the frame. An insulating resin is filled in the frame to protect the semiconductor element from external stress and humidity. A method of mounting a semiconductor device on a printed circuit board is further disclosed. In this method a sealing solid resin block is first sustained on a stopper portion provided on the inner wall of a frame surrounding a semiconductor element and bonding wires, and then melted to seal the semiconductor element and bonding wires.
Inventors
- 👤 Takemi Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:49
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W72/00; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
146 words
A method of manufacturing a semiconductor device, comprising the steps of: mounting a semiconductor element on a circuit board having a wiring pattern; connecting bonding wires between said semiconductor element and said wiring pattern; positioning a frame to extend upward from said circuit board to surround said bonding wires, said wiring pattern, and said semiconductor element, said frame having an inner wall and a stopper portion supported by said inner wall, said stopper portion being at a level more distant than a furthest portion of said semiconductor element and said bonding wires relative to said circuit board; placing a sealing solid resin block onto said stopper portion to hold said resin block in a position spaced from said semiconductor element and said bonding wires; and melting said sealing solid resin block to seal said semiconductor element, said bonding wires, and said wiring pattern within said frame.
Claim 2
Independent Claim
146 words
A method of manufacturing a semiconductor device, comprising the steps of: mounting a semiconductor element on a circuit board having a wiring pattern; connecting bonding wires between said semiconductor element and said wiring pattern; positioning a frame to extend upward from said circuit board to surround said bonding wires, said wiring pattern, and said semiconductor element, said frame having an inner wall and a stopper portion supported by said inner wall, said stopper portion being at a level more distant than a furthest portion of said semiconductor element and said bonding wires relative to said circuit board; placing a sealing solid resin block onto said stopper portion to hold said resin block in a position spaced from said semiconductor element and said bonding wires; and melting said sealing solid resin block to seal said semiconductor element, said bonding wires, and said wiring pattern within said frame.
Claim 3
Dependent Claim
14 words
A method according to claim 1, wherein said stopper portion comprises a stepped portion.
Claim 4
Dependent Claim
13 words
A method according to claim 1, wherein said stopper portion comprises a collar.
Claim 5
Dependent Claim
42 words
A method according to claim 1, wherein said stopper portion comprises a taper which is enlarged at portions of said taper at relatively greater distances from said circuit board than portions of said taper at relatively lesser distances from said circuit board.
Claim 6
Dependent Claim
18 words
A method according to claim 1, wherein said stopper portion extends along a portion of said inner wall.
Claim 7
Dependent Claim
22 words
A method according to claim 5, wherein said portion of said inner wall extends around the entire circumference of said inner wall.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-16 | 1992-02-15 | 1992-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-16 | 1996-02-15 | 1996-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-16 | 2000-02-15 | 2000-08-16 | $7700.00 | Window Closed / Lapsed |