US5001075A
Expired / Lapsed
US
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Fabrication of dielectrically isolated semiconductor device
Assignee: Motorola Solutions Inc
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Filing: 1989-04-03
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Granted: 1991-03-19
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Expires: 2009-04-03
Abstract
Abstract Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced. Recesses are formed in a (e.g., N + ) single crystal semiconductor wafer, the wafer surface is coated with a dielectric, and a thick polycrystalline semiconductor layer is deposited thereon to provide a support. The single crystal wafer is back-lapped to expose dielectrically isolated N + islands located between the original recesses. Depressions are etched in the N + islands and the exposed surface is covered by a more lightly doped (e.g., N - ) semiconductor layer which is, generally, single crystal above the N + islands and non-single crystal therebetween, and which at least fills the depressions. The structure is then planarized (e.g., by lapping and etching) to remove this non-single crystal material and give isolated single crystal islands having a surrounding N + periphery and an N - central epi region of well controlled thickness and a smooth outer surface suitable for device formation. Bipolar transistors of excellent properties are formed by providing a nested base and emitter within the central region. Other types of devices may also be formed. The surrounding N + periphery automatically provides a buried layer and buried layer contact.
Inventors
- 👤 Bernard W. Boland
- 👤 Paul W. Sanders
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:33
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
134 words
A method for forming a dielectrically isolated NPN bipolar transistor, comprising: providing a substrate having therein a uniformly doped, single crystal, N + semiconductor island extending substantially to an exposed surface of the substrate, wherein the N + island has a bottom and side adjacent an insulating portion of the substrate; then etching a cavity within the N + island, wherein the cavity is smaller and shallower than the island, so that a U-shaped portion of the uniformly doped N + island is left in place against the insulating portion of the substrate as a collector contact; substantially refilling the cavity with N - semiconductor to provide a collector having an exposed outer surface; and forming in the N - collector, a P base and N + emitter extending to the exposed outer surface.
Claim 2
Independent Claim
134 words
A method for forming a dielectrically isolated NPN bipolar transistor, comprising: providing a substrate having therein a uniformly doped, single crystal, N + semiconductor island extending substantially to an exposed surface of the substrate, wherein the N + island has a bottom and side adjacent an insulating portion of the substrate; then etching a cavity within the N + island, wherein the cavity is smaller and shallower than the island, so that a U-shaped portion of the uniformly doped N + island is left in place against the insulating portion of the substrate as a collector contact; substantially refilling the cavity with N - semiconductor to provide a collector having an exposed outer surface; and forming in the N - collector, a P base and N + emitter extending to the exposed outer surface.
Claim 3
Independent Claim
134 words
A method for forming a dielectrically isolated PNP bipolar transistor, comprising: providing a substrate having therein a uniformly doped, single crystal, P + semiconductor island extending substantially to an exposed surface of the substrate, wherein the P + island has a bottom and side adjacent an insulating portion of the substrate; then etching a cavity within the P + island, wherein the cavity is smaller and shallower than the island, so that a U-shaped portion of the uniformly doped P + island is left in place against the insulating portion of the substrate as a collector contact; substantially refilling the cavity with P - semiconductor to provide a collector having an exposed outer surface; and forming in the P - collector, a N base and P + emitter extending to the exposed outer surface.
Claim 4
Independent Claim
134 words
A method for forming a dielectrically isolated PNP bipolar transistor, comprising: providing a substrate having therein a uniformly doped, single crystal, P + semiconductor island extending substantially to an exposed surface of the substrate, wherein the P + island has a bottom and side adjacent an insulating portion of the substrate; then etching a cavity within the P + island, wherein the cavity is smaller and shallower than the island, so that a U-shaped portion of the uniformly doped P + island is left in place against the insulating portion of the substrate as a collector contact; substantially refilling the cavity with P - semiconductor to provide a collector having an exposed outer surface; and forming in the P - collector, a N base and P + emitter extending to the exposed outer surface.
Claim 5
Dependent Claim
33 words
The method of claim 1 wherein the substantially refilling step comprises, epitaxially growing N - semiconductor directly on the U-shaped portion of the uniformly doped N + island to substantially refill the cavity.
Claim 6
Dependent Claim
33 words
The method of claim 3 wherein the epitaxially growing step comprises epitaxially growing N - semiconductor directly on the U-shaped portion of the uniformly doped N + island without an intervening doping step.
Claim 7
Dependent Claim
147 words
The method of claim 1 wherein the providing step comprises (i) providing a single crystal semiconductor substrate having opposed first and second principal surfaces and with a uniformly doped N + region of a first predetermined thickness extending to the first surface, (ii) removing a portion of the N + region around a desired N + island location on the first surface to a first depth about equal the first thickness, (iii) providing an insulator on the first surface, (iv) providing a supporting material on the dielectric, and (v) removing semiconductor material from the second surface of the substrate until at least a first portion of the dielectric around the desired island location is revealed thereby forming a newly exposed second surface of the substrate containing a uniformly doped, single crystal, N + semiconductor island having a bottom and side adjacent a second portion of the insulator.
References Cited (Backward Citations)
US3461003A
Cited
US3407479A
Cited
US3457123A
Cited
US3431468A
Cited
US3508980A
Cited
US3876480A
Cited
US3929528A
Cited
US3902936A
Cited
JPS5243385A
Cited
JPS55154744A
Cited
JPS57130448A
Cited
JPS59186341A
Cited
JPS59186340A
Cited
US4566914A
Cited
JPS6017928A
Cited
US4649630A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-18 | 1994-09-17 | 1995-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-18 | 1998-09-17 | 1999-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-18 | 2002-09-17 | 2003-03-19 | $7700.00 | Window Closed / Lapsed |