Patent US4999800A successfully refreshed from Google Patents.
US4999800A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Floating point adder with pre-shifter
Assignee: ROTON BARRIER Inc
•
Filing: 1989-11-13
•
Granted: 1991-03-12
•
Expires: 2009-11-13
Abstract
Abstract The exponent computation part of a floating point adder and subtracter operates at high-speed. Prior to subtracting or adding of the mantissas, it is necessary to perform a computation on the exponents. The invention provides an exponent comparator and a pre-shifter responsive thereto for shifting the mantissa of at least one of the operands by at least one bit dependent on the comparison of at least the least significant bits of the exponents of the operands. The shift operation is carried out prior to the comparison of the most significant bits of the exponents of the operands. Once the most significant bits have been compared, the direction of final shifting can be determined and a further shift operation can be carried out, shifting either the unshifted or the pre-shifted mantissa by bit positions spaced in multiples of at least two.
Inventors
- 👤 Ari Birger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:55
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/485
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
262 words
A floating point computation device for performing computations on two operands each having an exponent and a mantissa, comprising: an exponent comparator for comparing the exponents of the two operands to provide an output having a least significant bit and a most significant bit: a pre-shifter for receiving the mantissa of each of the two operands and being coupled to the exponent comparator for receiving a least significant bit resulting from the comparing of the exponents, the pre-shifter shifting one of the mantissas a predetermined number of bit positions in response to the least significant bit having a predetermined logic value and otherwise not shifting either input operand, the pre-shifter providing the mantissa of the two operands in either shifted or non-shifted form: a decoder coupled to the exponent comparator for receiving a predetermined number of least significant bits of the output of the exponent comparator, said decoder providing both a difference of the exponents of the two input operands and a two's complement of the difference: a selector circuit coupled to both the exponent comparator and the decoder for selecting and outputting one of the difference of the exponents or the two's complement thereof as an output signal in response to the most significant bit resulting from the comparing of the exponents: and a shifter circuit coupled to the pre-shifter for receiving the mantissa of the two input operands in either shifted or non-shifted form, and shifting at least one of the two mantissas by a predetermined number of bits position in response to the output signal of the selector circuit.
Claim 2
Dependent Claim
262 words
A floating point computation device for performing computations on two operands each having an exponent and a mantissa, comprising: an exponent comparator for comparing the exponents of the two operands to provide an output having a least significant bit and a most significant bit: a pre-shifter for receiving the mantissa of each of the two operands and being coupled to the exponent comparator for receiving a least significant bit resulting from the comparing of the exponents, the pre-shifter shifting one of the mantissas a predetermined number of bit positions in response to the least significant bit having a predetermined logic value and otherwise not shifting either input operand, the pre-shifter providing the mantissa of the two operands in either shifted or non-shifted form: a decoder coupled to the exponent comparator for receiving a predetermined number of least significant bits of the output of the exponent comparator, said decoder providing both a difference of the exponents of the two input operands and a two's complement of the difference: a selector circuit coupled to both the exponent comparator and the decoder for selecting and outputting one of the difference of the exponents or the two's complement thereof as an output signal in response to the most significant bit resulting from the comparing of the exponents: and a shifter circuit coupled to the pre-shifter for receiving the mantissa of the two input operands in either shifted or non-shifted form, and shifting at least one of the two mantissas by a predetermined number of bits position in response to the output signal of the selector circuit.
Claim 3
Dependent Claim
31 words
A computation device according to claim 1 wherein the predetermined number of bit positions which the shifter circuit shifts at least one of the two mantissas is a multiple of two.
Claim 4
Dependent Claim
193 words
In a data processor having a floating point adder, a method of computation of two floating point operands, each having an exponent and a mantissa, comprising the steps of: coupling the exponents of said operands to a comparator and comparing the exponents of the two input operands to provide output compare bits; pre-shifting with a first shifting circuit at least one mantissa a predetermined odd number of bit positions in response to a least significant bit of the output compare bits having a predetermined logic value and otherwise not shifting either mantissa of the floating point operands: decoding a predetermined number of the output compare bits by providing both a difference of the exponents of the two input operands and a two's complement of the difference: selecting one of either the difference of the exponents or the two's complement thereof to provide as a control signal in response to a most significant bit resulting from the comparing of the exponents: and further shifting with a second shifting circuit at least one of the two mantissas by a number of bit positions which is a multiple of two in response to the control signal.
Claim 5
Dependent Claim
193 words
In a data processor having a floating point adder, a method of computation of two floating point operands, each having an exponent and a mantissa, comprising the steps of: coupling the exponents of said operands to a comparator and comparing the exponents of the two input operands to provide output compare bits; pre-shifting with a first shifting circuit at least one mantissa a predetermined odd number of bit positions in response to a least significant bit of the output compare bits having a predetermined logic value and otherwise not shifting either mantissa of the floating point operands: decoding a predetermined number of the output compare bits by providing both a difference of the exponents of the two input operands and a two's complement of the difference: selecting one of either the difference of the exponents or the two's complement thereof to provide as a control signal in response to a most significant bit resulting from the comparing of the exponents: and further shifting with a second shifting circuit at least one of the two mantissas by a number of bit positions which is a multiple of two in response to the control signal.
Claim 6
Dependent Claim
273 words
In a floating point adder of a data processor for adding and subtracting floating point operands, a circuit for performing computations on two input operands each having an exponent and a mantissa, comprising: an exponent comparator for receiving the exponent of each of the two input operands and comparing the exponents of the two input operands to provide output compare bits; first shifting means for receiving the mantissa of each of the two input operands and being coupled to the exponent comparator for receiving a least significant bit resulting from the comparing of the exponents, said first shifting means selectively shifting at least one mantissa a predetermined odd number of bit positions in response to the least significant bit having a predetermined logic value and otherwise not shifting either input operand; a decoder having an input coupled to a predetermined number of the output compare bits provided by the exponent comparator, said decoder providing both a difference of the exponents of the two input operands and a two's complement of the difference; a selector circuit coupled to both the exponent comparator and the decoder for selecting and outputting one of the difference of the exponents or the two's complement thereof as an output signal in response to a most significant bit resulting from the comparing of the exponents; and second shifting means coupled to the first shifting means for receiving the mantissa of the two operands in either shifted or non-shifted form, and shifting at least one of the two mantissas by a number of bit positions which is a multiple of two in response to the output signal of the selector circuit.
Claim 7
Dependent Claim
273 words
In a floating point adder of a data processor for adding and subtracting floating point operands, a circuit for performing computations on two input operands each having an exponent and a mantissa, comprising: an exponent comparator for receiving the exponent of each of the two input operands and comparing the exponents of the two input operands to provide output compare bits; first shifting means for receiving the mantissa of each of the two input operands and being coupled to the exponent comparator for receiving a least significant bit resulting from the comparing of the exponents, said first shifting means selectively shifting at least one mantissa a predetermined odd number of bit positions in response to the least significant bit having a predetermined logic value and otherwise not shifting either input operand; a decoder having an input coupled to a predetermined number of the output compare bits provided by the exponent comparator, said decoder providing both a difference of the exponents of the two input operands and a two's complement of the difference; a selector circuit coupled to both the exponent comparator and the decoder for selecting and outputting one of the difference of the exponents or the two's complement thereof as an output signal in response to a most significant bit resulting from the comparing of the exponents; and second shifting means coupled to the first shifting means for receiving the mantissa of the two operands in either shifted or non-shifted form, and shifting at least one of the two mantissas by a number of bit positions which is a multiple of two in response to the output signal of the selector circuit.
Claim 8
Dependent Claim
22 words
The circuit of claim 9 wherein the first shifting means shifts each mantissa of the two input operands by one bit position.
References Cited (Backward Citations)
US4807172A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-11 | 1994-09-10 | 1995-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-11 | 1998-09-10 | 1999-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-11 | 2002-09-10 | 2003-03-12 | $7700.00 | Window Closed / Lapsed |