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US4999312A Expired / Lapsed US ⏱️ 0.0 years remaining

Doping method using an oxide film and a nitride film on the trench wall to manufacture a semiconductor device and the manufactured device

Assignee: SK Hynix Inc
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Filing: 1989-08-16
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Granted: 1991-03-12
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Expires: 2009-08-16
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Abstract

Abstract A doping method using an oxide film and a nitride film on a trench wall as a protective film to prevent the impurity from diffusing into the silicon wafer adjacent to the outer wall and to enable the formation of a substantially flat interface between the first and the second trench to provide a smooth step difference between the first trench and the second trench is disclosed. A highly integrated semiconductor device having a trench comprising a first trench having a bottom and with a second trench formed in the bottom of the first trench with an interface between the first trench and the second trench characterized by the interface between the first and the second trench being substantially flat to provide a smooth step difference between the first trench and the second trench is also disclosed.

Inventors

  • 👤 Yong H. Yoon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 07:12
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0387; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; H10P50/00; H10P50/69; H10P50/691; H10P50/693; H10P50/694; H10P50/695; H10P76/00; H10P76/40; H10P76/408; H10P76/4085

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 445 words
A doping method for a side wall of a trench capacitor comprising: providing a silicon wafer; sequentially forming a mask layer including a first oxide layer, a nitride layer and a second oxide layer on the silicon wafer and then depositing a photoresist layer on the second oxide layer; forming a first mask pattern by removing a portion of the photoresist layer to expose a portion of the second oxide layer; forming a second mask pattern by removing the portion of the exposed second oxide layer, the nitride layer and first oxide layer underlying the exposed second oxide layer to expose the silicon wafer; removing any remaining photoresist layer; forming a first trench having an inner wall and an outer wall and a bottom in the silicon wafer exposed by the formation of the second mask pattern and then rinsing the first trench; depositing an oxide film on the inner wall and the bottom of the first trench and forming a nitride film on the entire surface of the oxide film, the mask layer including the second oxide layer of the mask layer; removing a portion of the oxide film and the nitride film from the bottom of the first trench concurrently with removing the nitride film formed on the second oxide layer of the mask layer with n anisotropic etching process, and then removing the second oxide layer beneath the nitride film; forming a second trench in the silicon wafer, exposed by removing a portion of the nitride and the oxide film, from the bottom of the first trench, and rinsing the second trench; depositing a dopant source on the entire surface of the inner wall of the second trench, on the nitride film and on the nitride layer, with the oxide film and the nitride film on the first trench wall providing a protective film to prevent the impurity of the dopant source from diffusing into the silicon wafer adjacent to the outer wall of the first trench; forming an impurity doped region in the silicon wafer adjacent to the outer wall of the second trench; forming an oxidation region on the inner and outer walls of the second trench by performing an oxidation process along the inner wall of the second trench having the impurity doped region on the outer wall thereof; and removing the nitride film and the oxide film formed on the inner wall of the first trench, and removing the oxidation region formed on the inner and outer wall of the second trench thereby providing a substantially flat interface between the first and second trench to form a smooth step difference between the first trench and the second trench.
Claim 2
Dependent Claim 445 words
A doping method for a side wall of a trench capacitor comprising: providing a silicon wafer; sequentially forming a mask layer including a first oxide layer, a nitride layer and a second oxide layer on the silicon wafer and then depositing a photoresist layer on the second oxide layer; forming a first mask pattern by removing a portion of the photoresist layer to expose a portion of the second oxide layer; forming a second mask pattern by removing the portion of the exposed second oxide layer, the nitride layer and first oxide layer underlying the exposed second oxide layer to expose the silicon wafer; removing any remaining photoresist layer; forming a first trench having an inner wall and an outer wall and a bottom in the silicon wafer exposed by the formation of the second mask pattern and then rinsing the first trench; depositing an oxide film on the inner wall and the bottom of the first trench and forming a nitride film on the entire surface of the oxide film, the mask layer including the second oxide layer of the mask layer; removing a portion of the oxide film and the nitride film from the bottom of the first trench concurrently with removing the nitride film formed on the second oxide layer of the mask layer with n anisotropic etching process, and then removing the second oxide layer beneath the nitride film; forming a second trench in the silicon wafer, exposed by removing a portion of the nitride and the oxide film, from the bottom of the first trench, and rinsing the second trench; depositing a dopant source on the entire surface of the inner wall of the second trench, on the nitride film and on the nitride layer, with the oxide film and the nitride film on the first trench wall providing a protective film to prevent the impurity of the dopant source from diffusing into the silicon wafer adjacent to the outer wall of the first trench; forming an impurity doped region in the silicon wafer adjacent to the outer wall of the second trench; forming an oxidation region on the inner and outer walls of the second trench by performing an oxidation process along the inner wall of the second trench having the impurity doped region on the outer wall thereof; and removing the nitride film and the oxide film formed on the inner wall of the first trench, and removing the oxidation region formed on the inner and outer wall of the second trench thereby providing a substantially flat interface between the first and second trench to form a smooth step difference between the first trench and the second trench.
Claim 3
Dependent Claim 30 words
The method of claim 1 wherein the impurity doped region in the silicon wafer adjacent to the outer wall of the second trench is formed by performing a drive-in process.

References Cited (Backward Citations)

US4569701A Cited
US4824793A Cited
US4676847A Cited
US4734384A Cited
GB2199696A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-03-11 1994-09-10 1995-03-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-03-11 1998-09-10 1999-03-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-03-11 2002-09-10 2003-03-12 $7700.00 Window Closed / Lapsed

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