US4996443A — Integrated circuit for level shift

Claim 1

Independent Claim 292 words

An integrated circuit for level shift, comprising a first series-connected circuit including a first MOS FET (P1) of one conductive type, a third MOS FET (N3) of another conductive type and a first MOS FET (N1) of the other conductive type which are connected in series in this order, and a second series-connected circuit including a second MOS FET (P2) of the one conductive type, a fourth MOS FET (N4) of the the other conductive type and a second MOS FET (N2) of the other conductive type which are connected in series in this order, said first series-connected circuit and said second series-connected circuit being connected in parallel to each other to constitute a parallel-connected unit, a gate of said first MOS FET of the one conductive type and a gate of said second MOS FET of the one conductive type being connected respectively to the output side and the input side of an inverter (INV1) connected to a low voltage electric power source, a gate of said third MOS FET of the other conductive type and a gate of said fourth MOS FET of the other conductive type both being connected to a reference voltage source (Vref), a gate of said first MOS FET of the other conductive type being connected to a common junction point of said fourth MOS FET of the other conductive type and said second MOS FET of the other conductive type, a gate of said second MOS FET of the other conductive type being connected to a common junction point of said third MOS FET of the other conductive type and said first MOS FET of the other conductive type, said parallel-connected unit being for connection to a high voltage electric power source (V DD ).

Claim 2

Dependent Claim 292 words

An integrated circuit for level shift, comprising a first series-connected circuit including a first MOS FET (P1) of one conductive type, a third MOS FET (N3) of another conductive type and a first MOS FET (N1) of the other conductive type which are connected in series in this order, and a second series-connected circuit including a second MOS FET (P2) of the one conductive type, a fourth MOS FET (N4) of the the other conductive type and a second MOS FET (N2) of the other conductive type which are connected in series in this order, said first series-connected circuit and said second series-connected circuit being connected in parallel to each other to constitute a parallel-connected unit, a gate of said first MOS FET of the one conductive type and a gate of said second MOS FET of the one conductive type being connected respectively to the output side and the input side of an inverter (INV1) connected to a low voltage electric power source, a gate of said third MOS FET of the other conductive type and a gate of said fourth MOS FET of the other conductive type both being connected to a reference voltage source (Vref), a gate of said first MOS FET of the other conductive type being connected to a common junction point of said fourth MOS FET of the other conductive type and said second MOS FET of the other conductive type, a gate of said second MOS FET of the other conductive type being connected to a common junction point of said third MOS FET of the other conductive type and said first MOS FET of the other conductive type, said parallel-connected unit being for connection to a high voltage electric power source (V DD ).

Claim 3

Dependent Claim 23 words

A circuit according to claim 1, wherein said one conductive type is P type, and wherein said other conductive type is N type.

Claim 4

Dependent Claim 131 words

A level shift circuit comprising: (a) first to third transistors (P1, N3, N1) which are connected in series to constitute a first circuit; (b) fourth to sixth transistors (P2, N4, N2) which are connected in series to constitute a second circuit, said first circuit and said second circuit being connected in parallel relative to a predetermined voltage V DD -V SS2 ); (c) first input means (INV1) for selectively causing one of said first and said fourth transistors to operate with a voltage lower than said predetermined voltage; (d) second input means (Vref) for inputting a common signal to said second and said fifth transistors; and (e) connecting means for connecting control electrodes of said third and said sixth transistors respectively to other electrodes of said sixth and said third transistors.

Claim 5

Dependent Claim 131 words

A level shift circuit comprising: (a) first to third transistors (P1, N3, N1) which are connected in series to constitute a first circuit; (b) fourth to sixth transistors (P2, N4, N2) which are connected in series to constitute a second circuit, said first circuit and said second circuit being connected in parallel relative to a predetermined voltage V DD -V SS2 ); (c) first input means (INV1) for selectively causing one of said first and said fourth transistors to operate with a voltage lower than said predetermined voltage; (d) second input means (Vref) for inputting a common signal to said second and said fifth transistors; and (e) connecting means for connecting control electrodes of said third and said sixth transistors respectively to other electrodes of said sixth and said third transistors.

Claim 6

Dependent Claim 19 words

A circuit according to claim 3, wherein said first and said fourth transistors are of the same conductive type.

Claim 7

Dependent Claim 32 words

A circuit according to claim 4, wherein said second, said third, said fifth and said sixth transistors are of the conductive type different from that of said first and said fourth transistors.

Claim 8

Dependent Claim 14 words

A circuit according to claim 3, wherein said first input means includes an inverter.

Claim 9

Dependent Claim 15 words

A circuit according to claim 3, wherein said second input means is a constant voltage.

Claim 10

Dependent Claim 16 words

A circuit according to claim 3, wherein said first to said sixth transistors are MOS FETs.

Claim 11

Dependent Claim 18 words

A circuit according to claim 4, wherein said first and said fourth transistors have a P type channel.

Claim 12

Dependent Claim 22 words

A circuit according to claim 5, wherein said second, said third, said fifth and said sixth transistors have an N type channel.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-02-25	1994-08-27	1995-02-26	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-02-25	1998-08-27	1999-02-26	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-02-25	2002-08-27	2003-02-26	$7700.00	Window Closed / Lapsed

Integrated circuit for level shift

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