Patent US4994893A successfully refreshed from Google Patents.
US4994893A
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Field effect transistor substantially coplanar surface structure
Assignee: Mitsubishi Electric Corp
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Filing: 1989-09-11
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Granted: 1991-02-19
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Expires: 2009-09-11
Abstract
Abstract A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.
Inventors
- 👤 Hiroji Ozaki
- 👤 Takahisa Eimori
- 👤 Yoshinori Tanaka
- 👤 Wataru Wakamiya
- 👤 Shinichi Satoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:28
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10B; H10B12/00; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
192 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having major surface, field shield conductor layers formed spaced apart from each other on the major surface of said semiconductor substrate through an insulating film and with the surface thereof being covered with the insulating film, a control gate conductor layer formed on the major surface of said semiconductor substrate between said field shield conductor layers through an insulating film and with the surface thereof being covered with the insulating film, an impurity region of a second conductivity type formed between each of said field shield conductor layers and said control gate conductor layer and on the major surface of said semiconductor substrate, and an interconnection layer formed so as to selectively fill a portion on an exposed major surface of said impurity region between each of said field shield conductor layers and said control gate conductor layer, wherein said interconnection layer is formed substantially coplanar with said field shield conductor layers and said control gate conductor layer and top surfaces of said field shield conductor layers are substantially coplanar with a top surface of said central gate conductor layer.
Claim 2
Dependent Claim
192 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having major surface, field shield conductor layers formed spaced apart from each other on the major surface of said semiconductor substrate through an insulating film and with the surface thereof being covered with the insulating film, a control gate conductor layer formed on the major surface of said semiconductor substrate between said field shield conductor layers through an insulating film and with the surface thereof being covered with the insulating film, an impurity region of a second conductivity type formed between each of said field shield conductor layers and said control gate conductor layer and on the major surface of said semiconductor substrate, and an interconnection layer formed so as to selectively fill a portion on an exposed major surface of said impurity region between each of said field shield conductor layers and said control gate conductor layer, wherein said interconnection layer is formed substantially coplanar with said field shield conductor layers and said control gate conductor layer and top surfaces of said field shield conductor layers are substantially coplanar with a top surface of said central gate conductor layer.
Claim 3
Dependent Claim
28 words
The semiconductor device according to claim 1, wherein said interconnection layer comprises a film selectively formed by chemical vapor deposition on the major surface of said impurity region.
Claim 4
Dependent Claim
14 words
The semiconductor device according to claim 2, wherein said film comprises a metal film.
Claim 5
Dependent Claim
15 words
The semiconductor device according to claim 2, wherein said film comprises a metal silicide film.
Claim 6
Dependent Claim
32 words
The semiconductor device according to claim 1, wherein each of said field shield conductor layers has a surface exposed, and said interconnection layer comprises a conductor layer selectively formed on its surface.
Claim 7
Dependent Claim
25 words
The semiconductor device according to claim 5, which further comprises an interconnection layer formed so as to contact with the surface of said interconnection layer.
Claim 8
Dependent Claim
35 words
The semiconductor device according to claim 1, wherein said semiconductor device comprises a plurality of field effect devices formed, isolated by said field shield conductor layers each having a surface covered with an insulating film.
Claim 9
Dependent Claim
52 words
The semiconductor device according to claim 7, wherein each of said field effect devices comprises said control gate conductor layer and said impurity region, said control gate conductor layer is a gate electrode, and said impurity region has one and the other impurity regions constituting a source region and a drain region.
Claim 10
Dependent Claim
30 words
The semiconductor device according to claim 8, wherein said semiconductor device further comprises a capacitance portion connected to the field effect device on the major surface of said semiconductor substrate.
Claim 11
Dependent Claim
55 words
The semiconductor device according to claim 9, wherein said capacitance portion has a stacked structure comprising a conductive film formed in contact with one of said impurity regions, an insulating film formed on the surface of the conductive film, and a conductive film formed on the insulating film, to constitute a capacitor for storing charges.
Claim 12
Dependent Claim
29 words
The semiconductor device according to claim 10, wherein said capacitance portion is formed so as to extend above said field shield conductor layers and said control gate conductor layer.
Claim 13
Dependent Claim
160 words
A semiconductor device comprising: a plurality of MOS transistors formed on a substrate and each having a pair of source/drain regions and a gate electrode, an area of source/drain regions in at least one of said MOS transistors being larger than that of the other MOS transistors; an insulator layer formed on the surface of said substrate and said gate electrodes of MOS transistors and having a plurality of holes thereof positioned at said source/drain region and extending to the surface of said substrate, an area of one said holes positioned at a source/drain region of said at least one of said MOS transistors being larger than an area of a hole positioned at another MOS transistor; a plurality of refractory metal regions filled in said plurality of holes, a thickness of said refractory metal regions being substantially the same as a depth of said holes, and a plurality of a wiring layers connected to said refractory metal regions, respectively.
Claim 14
Dependent Claim
160 words
A semiconductor device comprising: a plurality of MOS transistors formed on a substrate and each having a pair of source/drain regions and a gate electrode, an area of source/drain regions in at least one of said MOS transistors being larger than that of the other MOS transistors; an insulator layer formed on the surface of said substrate and said gate electrodes of MOS transistors and having a plurality of holes thereof positioned at said source/drain region and extending to the surface of said substrate, an area of one said holes positioned at a source/drain region of said at least one of said MOS transistors being larger than an area of a hole positioned at another MOS transistor; a plurality of refractory metal regions filled in said plurality of holes, a thickness of said refractory metal regions being substantially the same as a depth of said holes, and a plurality of a wiring layers connected to said refractory metal regions, respectively.
References Cited (Backward Citations)
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