Patent US4994872A successfully refreshed from Google Patents.
US4994872A
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Insulated gate static induction transistor and integrated circuit including same
Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
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Filing: 1988-07-29
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Granted: 1991-02-19
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Expires: 2008-07-29
Abstract
Abstract An insulated-gate static induction transistor is formed by establishing a potential barrier in a semiconductor region of one conductivity type between the source and the drain regions of the other conductivity type. The height of the potential barrier should be sensitive to the drain voltage as well as to the gate voltage. Therefore, the semiconductor region should have a low impurity concentration and short length. The potential barrier can be established by varying the field effect of the gate voltage in the semiconductor region and/or by the built-in potential between the source region and the semiconductor region.
Inventors
- 👤 Jun-ichi Nishizawa
- 👤 Tadahiro Ohmi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D30/202; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D62/393; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H10D84/85; H10D89/00; H10D89/211; H10D89/213; H10D89/217; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513; H10D64/514; H10D64/516
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
330 words
A semiconductor integrated circuit including at least two semiconductor elements at least one of which is formed with an insulated-gate static induction transistor, said transistor comprising: a source semiconductor region of a first conductivity type including a portion having a high impurity concentration; a source ohmic contact electrode formed on said source semiconductor region; a drain semiconductor region of said first conductivity type including a portion having a high impurity concentration; a drain ohmic contact electrode formed on said drain semiconductor region; at least one channel semiconductor region of a second conductivity type opposite to said first conductivity type, disposed between said source and drain regions and having a low impurity concentration; an insulated-gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; said source and drain regions defining a controlled current path therebetween through a portion of said channel semiconductor region; said source and channel regions including adjacent recessed portions wherein said insulated-gate structure is formed; said channel region including at least first and second adjacent layers, said first layer having an impurity concentration higher than said second layer and the impurity concentration of the channel region under said insulating film being non-uniform overall; said channel region including a first channel portion disposed adjacent to said source region and a second channel portion disposed between said first channel portion and said drain region, adjacent to said first channel portion, said first channel portion having an impurity concentration greater than the impurity concentration of said second channel portion; and means, including said insulating gate structure and said channel region with predetermined channel length and carrier concentration, for enabling the formation of a two-dimensional potential ridge coupled to both said gate electrode and said drain region in said first channel portion, whereby said transistor exhibits nonsaturating drain current-drain voltage characteristics which obey the exponential law; said integrated circuit constituting at least one invertor including said insulated-gate static induction transistor.
Claim 2
Dependent Claim
330 words
A semiconductor integrated circuit including at least two semiconductor elements at least one of which is formed with an insulated-gate static induction transistor, said transistor comprising: a source semiconductor region of a first conductivity type including a portion having a high impurity concentration; a source ohmic contact electrode formed on said source semiconductor region; a drain semiconductor region of said first conductivity type including a portion having a high impurity concentration; a drain ohmic contact electrode formed on said drain semiconductor region; at least one channel semiconductor region of a second conductivity type opposite to said first conductivity type, disposed between said source and drain regions and having a low impurity concentration; an insulated-gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; said source and drain regions defining a controlled current path therebetween through a portion of said channel semiconductor region; said source and channel regions including adjacent recessed portions wherein said insulated-gate structure is formed; said channel region including at least first and second adjacent layers, said first layer having an impurity concentration higher than said second layer and the impurity concentration of the channel region under said insulating film being non-uniform overall; said channel region including a first channel portion disposed adjacent to said source region and a second channel portion disposed between said first channel portion and said drain region, adjacent to said first channel portion, said first channel portion having an impurity concentration greater than the impurity concentration of said second channel portion; and means, including said insulating gate structure and said channel region with predetermined channel length and carrier concentration, for enabling the formation of a two-dimensional potential ridge coupled to both said gate electrode and said drain region in said first channel portion, whereby said transistor exhibits nonsaturating drain current-drain voltage characteristics which obey the exponential law; said integrated circuit constituting at least one invertor including said insulated-gate static induction transistor.
Claim 3
Dependent Claim
31 words
A semiconductor integrated circuit as in claim 1 wherein said conductive gate electrode includes a first section having a first work function and a second section having a second work function.
Claim 4
Dependent Claim
23 words
A semiconductor integrated circuit as in claim 2 wherein said first section is disposed closer to said source region than said second section.
Claim 5
Dependent Claim
36 words
A semiconductor integrated circuit as in claim 1 wherein said insulating film includes a first section having a first dielectric constant and a second section having a second dielectric constant larger than said first dielectric constant.
Claim 6
Dependent Claim
23 words
A semiconductor integrated circuit as in claim 4 wherein said first section is disposed closer to said source region than said second region.
Claim 7
Dependent Claim
346 words
A semiconductor integrated circuit including at least two semiconductor elements at least one of which is formed with an insulated-gate static induction transistor comprising: a source semiconductor region of a first conductivity type including a portion having a high impurity concentration; a source ohmic contact electrode formed on said source semiconductor region; a drain semiconductor region of said first conductivity type including a portion having a high impurity concentration; a drain ohmic contact electrode formed on said drain semiconductor region; at least one channel semiconductor region of a second conductivity type opposite to said first conductivity type, disposed between said source and drain regions and having a low impurity concentration; an insulated-gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; said source and drain regions defining a controlled current path therebetween through a portion of said channel semiconductor region; said source and channel regions including adjacent recessed portions wherein said insulated-gate structure is formed; said channel region including at least first and second adjacent layers, said first layer having an impurity concentration higher than said second layer; said channel region including a first channel portion disposed adjacent to said source region and a second channel portion disposed between said first channel portion and said drain region, adhjacnet to said first channel portion, said first channel portion having an impurity concentration greater than the impurity concentration of said second channel portion; means, including said insulated gate structure and said channel region with predetermined channel length and carrier concentration, for enabling the formation of a two-dimensional potential ridge coupled to both said gate electrode and said drain region in said first channel portion, whereby said transistor exhibits nonsaturating drain current-drain voltage characteristics which obey the exponential law; and said integrated circuit constituting at least one injection integrated logic circuit including an injector transistor having at least one current output region, and an invertor transistor formed with said insulated-gate static induction transistor having said gate electrode connected to said current output region of said injector transistor.
Claim 8
Dependent Claim
346 words
A semiconductor integrated circuit including at least two semiconductor elements at least one of which is formed with an insulated-gate static induction transistor comprising: a source semiconductor region of a first conductivity type including a portion having a high impurity concentration; a source ohmic contact electrode formed on said source semiconductor region; a drain semiconductor region of said first conductivity type including a portion having a high impurity concentration; a drain ohmic contact electrode formed on said drain semiconductor region; at least one channel semiconductor region of a second conductivity type opposite to said first conductivity type, disposed between said source and drain regions and having a low impurity concentration; an insulated-gate structure including an insulating film formed on said channel semiconductor region and a conductive gate electrode formed on said insulating film; said source and drain regions defining a controlled current path therebetween through a portion of said channel semiconductor region; said source and channel regions including adjacent recessed portions wherein said insulated-gate structure is formed; said channel region including at least first and second adjacent layers, said first layer having an impurity concentration higher than said second layer; said channel region including a first channel portion disposed adjacent to said source region and a second channel portion disposed between said first channel portion and said drain region, adhjacnet to said first channel portion, said first channel portion having an impurity concentration greater than the impurity concentration of said second channel portion; means, including said insulated gate structure and said channel region with predetermined channel length and carrier concentration, for enabling the formation of a two-dimensional potential ridge coupled to both said gate electrode and said drain region in said first channel portion, whereby said transistor exhibits nonsaturating drain current-drain voltage characteristics which obey the exponential law; and said integrated circuit constituting at least one injection integrated logic circuit including an injector transistor having at least one current output region, and an invertor transistor formed with said insulated-gate static induction transistor having said gate electrode connected to said current output region of said injector transistor.
Claim 9
Dependent Claim
31 words
A semiconductor integrated circuit as in claim 6 wherein said conductive gate electrode includes a first section having a first work function and a second section having a second work function.
Claim 10
Dependent Claim
23 words
A semiconductor integrated circuit as in claim 7 wherein said first section is disposed closer to said source region than said second section.
Claim 11
Dependent Claim
36 words
A semiconductor integrated circuit as in claim 6 wherein said insulating film includes a first section having a first dielectric constant and a second section having a second dielectric constant larger than said first dielectric constant.
Claim 12
Dependent Claim
23 words
A semiconductor integrated circuit as in claim 9 wherein said first section is disposed closer to said source region than said second region.
References Cited (Backward Citations)
US4814843A
Cited
US4317127A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |