US4994730A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current source circuit with complementary current mirrors
Assignee: STMicroelectronics SRL
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Filing: 1989-12-11
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Granted: 1991-02-19
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Expires: 2009-12-11
Abstract
Abstract A current source circuit capable of generating two currents of opposite polarities. In order to generate the two currents, the circuit comprises a current source stage including a current mirror and feeding a first output current and an inverter stage connected to the source stage and generating a second output current with opposite polarity with respect to the first. The inverter stage comprises a current mirror and a variable current source defining a control electrode. In order to eliminate the differences in the amplitude of the output currents, the inverter stage comprises a memory element connected to the control electrode so as to store an electrode controlling signal. Switch elements are furthermore interposed between the first output and the second output so as to short-circuit them during the trimming step so that the two output currents are equal to one another while the memory element memorizes the control signal. This signal remains stored during the normal operation of the circuit.
Inventors
- 👤 Domenico Rossi
- 👤 Ermes Viani
- 👤 Guido Torelli
- 👤 Franco Maloberti
- 👤 Carla Vacchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:54
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
153 words
A current source circuit comprising a current source stage defining a first output and generating a first output current and an inverter stage connected to said source stage and defining a second output, said inverted stage generating a second output current with opposite polarity with respect to said first output current, said inverter stage comprising a variable current source defining a control electrode and a memory element connected to said control electrode and adapted to store a control signal for said variable current source, said current source circuit further comprising switch means interposed between said first and second outputs, said switch means being closed during a trimming step of said current source circuit, causing said first and second outputs to be short-circuited, said control signal to assume a value corresponding to an amplitude equivalence of said first and second output currents and said memory element to store said value of said control signal.
Claim 2
Dependent Claim
153 words
A current source circuit comprising a current source stage defining a first output and generating a first output current and an inverter stage connected to said source stage and defining a second output, said inverted stage generating a second output current with opposite polarity with respect to said first output current, said inverter stage comprising a variable current source defining a control electrode and a memory element connected to said control electrode and adapted to store a control signal for said variable current source, said current source circuit further comprising switch means interposed between said first and second outputs, said switch means being closed during a trimming step of said current source circuit, causing said first and second outputs to be short-circuited, said control signal to assume a value corresponding to an amplitude equivalence of said first and second output currents and said memory element to store said value of said control signal.
Claim 3
Dependent Claim
24 words
A circuit according to claim 1, wherein said variable current source comprises a MOS transistor having a gate electrode connected to said memory element.
Claim 4
Dependent Claim
13 words
A circuit according to claim 1, wherein said memory element comprises a capacitor.
Claim 5
Dependent Claim
48 words
A circuit according to claim 1, wherein said switch means comprise a first switch interposed between said first output of said current source stage and said second output of said inverter stage, said circuit further comprising a second switch interposed between said second output and said memory element.
Claim 6
Dependent Claim
34 words
A circuit according to claim 4, further comprising a third switch interposed between said current source stage and said first output and a fourth switch interposed between said inverter stage and said second output.
Claim 7
Dependent Claim
48 words
A circuit according to claim 4, further comprising an operational amplifier interposed between said second output and said second switch, said operational amplifier having an inverting input connected to said second output, a non-inverting input connected to a reference voltage and an output connected to said second switch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |