Patent US4989207A successfully refreshed from Google Patents.
US4989207A
Expired / Lapsed
US
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Automatic verification of kernel circuitry based on analysis of memory accesses
Assignee: Fluke Corp
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Filing: 1988-11-23
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Granted: 1991-01-29
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Expires: 2008-11-23
Abstract
Abstract A method and apparatus for providing automatic verification of the kernel circuitry of a microprocessor-based system in which the microprocessor (μP) include an instruction prefetch feature. During testing by memory emulation, the memory addresses accessed by the μP are evaluated as to type of access, address and data size in accordance with a test program and a corresponding checking table to determine if such accesses are consistent with a funtional μP of the same type. Other data structures such as flags and pointers are provided to enhance the verification operation and use of the checking table.
Inventors
- 👤 John D. Polstra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:16
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/2273
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
149 words
A method for verification of a unit under test having a microprocessor including prefetch logic comprising the steps of providing an emulation memory for testing kernel circuitry of said unit under test, loading a test program and corresponding checking table into said emulation memory, causing said microprocessor to execute said test program, monitoring the address of each memory access during execution of said test program, identifying each address accessed as one of at least an instruction access and a data access, determining if the address of each instruction access is greater than the preceding instruction access address, determining if the address of each data access is greater than the preceding data access address, determining if the address of each data access corresponds to a location of data specified in the most recently accessed instruction, and establishing verification of said kernel circuitry based upon the results of said determining steps.
Claim 2
Independent Claim
149 words
A method for verification of a unit under test having a microprocessor including prefetch logic comprising the steps of providing an emulation memory for testing kernel circuitry of said unit under test, loading a test program and corresponding checking table into said emulation memory, causing said microprocessor to execute said test program, monitoring the address of each memory access during execution of said test program, identifying each address accessed as one of at least an instruction access and a data access, determining if the address of each instruction access is greater than the preceding instruction access address, determining if the address of each data access is greater than the preceding data access address, determining if the address of each data access corresponds to a location of data specified in the most recently accessed instruction, and establishing verification of said kernel circuitry based upon the results of said determining steps.
Claim 3
Independent Claim
155 words
A method for verification of a unit under test having a microprocessor including prefetch logic comprising the steps of providing an emulation memory for testing kernel circuitry of said unit under test, loading a test program and corresponding checking table into said emulation memory, causing said microprocessor to execute said test program, monitoring the address of each memory access during execution of said test program, identifying each address accessed as one of at least an instruction access or a data access, determining if the address of each instruction access is greater than the preceding instruction access address, determining if the address of each data access is greater than the preceding data access address, determining if the address of each data access corresponds to a location of data specified in the most recently accessed instruction, and preventing verification of said kernel circuitry if the conditions specified in any one of said determining steps is not met.
Claim 4
Independent Claim
155 words
A method for verification of a unit under test having a microprocessor including prefetch logic comprising the steps of providing an emulation memory for testing kernel circuitry of said unit under test, loading a test program and corresponding checking table into said emulation memory, causing said microprocessor to execute said test program, monitoring the address of each memory access during execution of said test program, identifying each address accessed as one of at least an instruction access or a data access, determining if the address of each instruction access is greater than the preceding instruction access address, determining if the address of each data access is greater than the preceding data access address, determining if the address of each data access corresponds to a location of data specified in the most recently accessed instruction, and preventing verification of said kernel circuitry if the conditions specified in any one of said determining steps is not met.
Claim 5
Dependent Claim
38 words
A method according to claim 1, including the step of providing flags corresponding to said at least one of said instruction access and data access for indicating whether an instruction access or a data access is possible, respectively.
Claim 6
Dependent Claim
39 words
A method according to claim 3, wherein at least one said determining step includes the steps of determining if a said corresponding flag is set and determining if the address accessed corresponds to an address in said checking table.
Claim 7
Dependent Claim
31 words
A method according to claim 1, wherein data is provided in said checking table corresponding to a data access address and an instruction address in correspondence with to said test program.
Claim 8
Dependent Claim
25 words
A method according to claim 5, wherein said data in said checking table is further provided with data size information corresponding to said test program.
Claim 9
Independent Claim
185 words
An apparatus for verification of a unit under test having a microprocessor including prefetch logic comprising: an emulation memory means for testing kernel circuitry of said unit under test, loading means coupled to said emulation memory means for loading a test program and corresponding checking table into said emulation memory, and initialization means coupled to said microprocessor for causing said microprocessor to execute said test program, wherein said emulation memory means includes means for monitoring the address of each memory access during execution of said test program, identification means for identifying each address accessed as one of at least an instruction access and a data access, first comparison means for comparing each address of each instruction access with the preceding instruction access address, second comparison means for comparing each address of each data access with the preceding data access address, determination means for determining if the address of each data access corresponds to a location of data specified in the most recently accessed instruction, and means responsive to said first and second comparison means and said determination means for establishing verification of said kernel circuitry.
Claim 10
Independent Claim
185 words
An apparatus for verification of a unit under test having a microprocessor including prefetch logic comprising: an emulation memory means for testing kernel circuitry of said unit under test, loading means coupled to said emulation memory means for loading a test program and corresponding checking table into said emulation memory, and initialization means coupled to said microprocessor for causing said microprocessor to execute said test program, wherein said emulation memory means includes means for monitoring the address of each memory access during execution of said test program, identification means for identifying each address accessed as one of at least an instruction access and a data access, first comparison means for comparing each address of each instruction access with the preceding instruction access address, second comparison means for comparing each address of each data access with the preceding data access address, determination means for determining if the address of each data access corresponds to a location of data specified in the most recently accessed instruction, and means responsive to said first and second comparison means and said determination means for establishing verification of said kernel circuitry.
Claim 11
Dependent Claim
43 words
An apparatus according to claim 7, wherein said emulation memory means further includes means for containing flags corresponding to said at least one of said instruction access and data access for indicating whether an instruction access or a data access is possible, respectively.
Claim 12
Dependent Claim
26 words
An apparatus according to claim 8, wherein at least one of said first and second comparison means is enabled by a corresponding one of said flags.
Claim 13
Dependent Claim
28 words
An apparatus according to claim 7, wherein said checking table includes data corresponding to a data access address and an instruction address in correspondence with said test program.
Claim 14
Dependent Claim
20 words
An apparatus according to claim 10, wherein said checking table further includes data size information corresponding to said test program.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |