Data processing device having direct memory access with improved transfer control

Claim 2

A microcomputer, comprising: a central processing unit for performing data processing instructions; a bus, connected to said central processing units; a DMA control register connected to said central processing unit for storing a start code of at least two bits; and a DMA controller, connected to said bus and to said DMA control register, for reading data from said bus by placing a source memory address signal thereupon and receiving data therefrom, and for writing data to said bus by placing a destination memory address signal thereupon and presenting data thereto, said reading and writing repetitively performed constituting a DMA transfer of a block, wherein said DMA controller begins said DMA transfer responsive to a first value of said start code, said DMA controller further operable in selectable ways to stop said DMA transfer including a first way that aborts said DMA transfer upon completion of a next instance of said writing responsive to entry of a second value of said start code into said DMA control register during a read in said DMA transfer, and a second way that aborts said DMA transfer responsive to entry of a third value of said start code.

Claim 3

The microcomputer of claim 1, wherein said DMA controller aborts said DMA transfer upon completion of the current reading or writing step responsive to a fourth value of said start code.

Claim 4

The microcomputer of claim 1, wherein said DMA control register further is for storing a status code written thereto by said DMA controller, said status code indicating the status of the DMA transfer being performed by said DMA controller.

Claim 5

The microcomputer of claim 3, wherein a first value of said status code indicates that said DMA controller has completed the reading of data from said bus.

Claim 6

The microcomputer of claim 4, wherein a second value of said status code indicates that said DMA controller has completed the writing of data to said bus.

Claim 7

The microcomputer of claim 1, further comprising a memory connected to said bus, which is addressable by an address signal on said bus and which communicates data to and from said bus.

Claim 8

The microcomputer of claim 6, further comprising a peripheral port connected to said bus and an external memory connected to said peripheral port.

Claim 9

The microcomputer of claim 1, further comprising a peripheral port connected to said bus and an external memory connected to said peripheral port.

Claim 10

A data processing system comprising: a memory; an external bus connected to said memory; and a microcomputer, comprising: a central processing unit for performing data processing instructions; an internal bus, connected to said central processing unit; a memory port, connected between said internal bus and said external bus, for communicating address and data signals therebetween; a DMA control register connected to said central processing unit for storing a start code of at least two bits; and a DMA controller, connected to said internal bus and to said DMA control register, for reading data from said internal bus by placing a source memory address signal thereupon and receiving data therefrom, and for writing data to said internal bus by placing a destination memory address signal thereupon and presenting data thereto, said reading and writing repetitively performed constituting a DMA transfer of a block, wherein said DMA controller begins said DMA transfer responsive to a first value of said start code, said DMA controller further operable in selectable ways to stop said DMA transfer including a first way that aborts said DMA transfer upon completion of a next instance of said writing responsive to entry of a second value of said start code into said DMA control register during a read in said DMA transfer, and a second way that aborts said DMA transfer responsive to entry of a third value of said start code; wherein said memory is addressable by said DMA controller.

Claim 11

A data processing system comprising: a memory; an external bus connected to said memory; and a microcomputer, comprising: a central processing unit for performing data processing instructions; an internal bus, connected to said central processing unit; a memory port, connected between said internal bus and said external bus, for communicating address and data signals therebetween; a DMA control register connected to said central processing unit for storing a start code of at least two bits; and a DMA controller, connected to said internal bus and to said DMA control register, for reading data from said internal bus by placing a source memory address signal thereupon and receiving data therefrom, and for writing data to said internal bus by placing a destination memory address signal thereupon and presenting data thereto, said reading and writing repetitively performed constituting a DMA transfer of a block, wherein said DMA controller begins said DMA transfer responsive to a first value of said start code, said DMA controller further operable in selectable ways to stop said DMA transfer including a first way that aborts said DMA transfer upon completion of a next instance of said writing responsive to entry of a second value of said start code into said DMA control register during a read in said DMA transfer, and a second way that aborts said DMA transfer responsive to entry of a third value of said start code; wherein said memory is addressable by said DMA controller.

Claim 12

The system of claim 9, wherein said DMA controller aborts said DMA transfer upon completion of the current reading or writing step responsive to a fourth value of said start code.

Claim 13

The system of claim 9, wherein said DMA control register further is for storing a status code written thereto by said DMA controller, said status code indicating the status of the DMA transfer being performed by said DMA controller.

Claim 14

The system of claim 11, wherein a first value of said status code indicates that said DMA controller has completed the reading of data from said bus.

Claim 15

The system of claim 12, wherein a second value of said status code indicates that said DMA controller has completed the writing of data to said bus.

Claim 16

The system of claim 9, wherein said microcomputer further comprises an internal memory connected to said internal bus, said internal memory addressable by an address signal on said internal bus.

Claim 17

The system of claim 9, further comprising: an interrupt line, connected between said memory and said microcomputer for communicating an interrupt signal from said memory to said microcomputer; wherein said microcomputer further comprises: a central processing unit interrupt enable register, connected to said central processing unit, for storing a CPU interrupt enable code; and a DMA interrupt enable register, connected to said central processing unit, for storing a DMA interrupt enable code; wherein said DMA control register is further for storing a synchronization code; and wherein said DMA controller suspends said DMA transfer responsive to a first value of said synchronization code in said DMA control register until an interrupt signal occurs on said interrupt line from said memory when said DMA interrupt enable code and said CPU interrupt enable code represent that the interrupt signal is for said DMA controller and not said central processing unit.

Claim 18

The system of claim 15, wherein said DMA controller suspends said DMA transfer until an interrupt signal for said DMA controller occurs on said interrupt line from said memory between reading and writing responsive to said first value of said synchronization code, and alternatively suspends said DMA transfer until an interrupt signal for said DMA controller occurs on said interrupt line from said memory between writing and reading responsive to a second value of said synchronization code.

Claim 19

The system of claim 16, wherein said DMA controller suspends said DMA transfer until an interrupt signal for said DMA controller occurs on said interrupt line from said memory between reading and writing and between writing and reading responsive to a third value of said synchronization code.

Claim 20

A microcomputer, comprising: a central processing unit for performing data processing instructions; an internal bus, connected to said central processing unit; an interrupt terminal, connected to said central processing unit, for receiving an interrupt signal to said microcomputer; a CPU interrupt enable register, connected to said central processing unit, for storing a CPU interrupt enable code; a DMA interrupt enable register, connected to said central processing unit, for storing a DMA interrupt enable code; a DMA control register for storing a synchronization code; and a DMA controller, connected to said internal bus and to said DMA control register, for reading data from said internal bus by placing a source memory address signal thereupon and receiving data therefrom, and for writing data to said internal bus by placing a destination memory address signal thereupon and presenting data thereto, said reading and writing repetitively performed constituting a DMA transfer of a block, wherein said DMA controller suspends said DMA transfer responsive to a first value of said synchronization code in said DMA control register until an interrupt signal occurs at said interrupt terminal when said DMA interrupt enable code and said CPU interrupt enable code represent that the interrupt signal is for said DMA controller and not said central processing unit.

Claim 21

A microcomputer, comprising: a central processing unit for performing data processing instructions; an internal bus, connected to said central processing unit; an interrupt terminal, connected to said central processing unit, for receiving an interrupt signal to said microcomputer; a CPU interrupt enable register, connected to said central processing unit, for storing a CPU interrupt enable code; a DMA interrupt enable register, connected to said central processing unit, for storing a DMA interrupt enable code; a DMA control register for storing a synchronization code; and a DMA controller, connected to said internal bus and to said DMA control register, for reading data from said internal bus by placing a source memory address signal thereupon and receiving data therefrom, and for writing data to said internal bus by placing a destination memory address signal thereupon and presenting data thereto, said reading and writing repetitively performed constituting a DMA transfer of a block, wherein said DMA controller suspends said DMA transfer responsive to a first value of said synchronization code in said DMA control register until an interrupt signal occurs at said interrupt terminal when said DMA interrupt enable code and said CPU interrupt enable code represent that the interrupt signal is for said DMA controller and not said central processing unit.

Claim 22

The microcomputer of claim 18, wherein said DMA controller suspends said DMA transfer until an interrupt signal for said DMA controller occurs at said interrupt terminal between reading and writing responsive to said first value of said synchronization code, and alternatively suspends said DMA transfer until an interrupt signal for said DMA controller occurs at said interrupt terminal between writing and reading responsive to a second value of said synchronization code.

Claim 23

The microcomputer of claim 19, wherein said DMA controller suspends said DMA transfer until an interrupt signal for said DMA controller occurs at said interrupt terminal between reading and writing and between writing and reading responsive to a third value of said synchronization code.

Claim 24

The microcomputer of claim 18, wherein said DMA control register is further for storing a start code of at least two bits; and wherein said DMA controller begins said DMA transfer responsive to a first value of said start code, said DMA controller further operable in selectable ways to stop said DMA transfer including a first way that aborts said DMA transfer upon completion of a next instance of said writing responsive to entry of a second value of said start code into said DMA control register during a read in said DMA transfer, and a second way that aborts said DMA transfer responsive to entry of a third value of said start code.

Claim 25

The microcomputer of claim 21, wherein said DMA controller aborts said DMA transfer upon completion of the current reading or writing step responsive to a fourth value of said start code.

Claim 26

The microcomputer of claim 21, wherein said DMA control register further is for storing a status code written thereto by said DMA controller, said status code indicating the status of the DMA transfer being performed by said DMA controller.

Claim 27

The microcomputer of claim 22, wherein a first value of said status code indicates that said DMA controller has completed the reading of data from said internal bus.

Claim 28

The microcomputer of claim 24, wherein a second value of said status code indicates that said DMA controller has completed the writing of data to said internal bus.

Claim 29

The microcomputer of claim 21, further comprising a memory connected to said internal bus, which is addressable by an address signal on said internal bus and which communicates data to and from said internal bus.

Claim 30

The microcomputer of claim 26, further comprising a peripheral port connected to said internal bus and an external memory connected to said peripheral port.

Claim 31

The microcomputer of claim 21, further comprising a peripheral port connected to said internal bus and an external memory connected to said peripheral port.

Claim 32

A microcomputer system comprising: a central processing unit arranged to execute data processing instructions and produce digital signals; a memory for storing a block of data, the memory connected to said central processing unit; a peripheral device to which the block of data from said memory is to be transferred; and a direct memory access (DMA) controller connected to said central processing unit, said memory and said peripheral device, said DMA controller including a DMA control register and a DMA control circuit responsive to a first code entered from the microcomputer system into said DMA control register to start transferring the block, and then upon entry of a second code into the DMA control register during the transfer, to stop the transfer operation within the block in a manner defined by the second code and then start in sequence with a succeeding DMA operation in response to subsequent entry of the first code into the DMA control register.

Claim 33

A microcomputer system comprising: a central processing unit arranged to execute data processing instructions and produce digital signals; a memory for storing a block of data, the memory connected to said central processing unit; a peripheral device to which the block of data from said memory is to be transferred; and a direct memory access (DMA) controller connected to said central processing unit, said memory and said peripheral device, said DMA controller including a DMA control register and a DMA control circuit responsive to a first code entered from the microcomputer system into said DMA control register to start transferring the block, and then upon entry of a second code into the DMA control register during the transfer, to stop the transfer operation within the block in a manner defined by the second code and then start in sequence with a succeeding DMA operation in response to subsequent entry of the first code into the DMA control register.

Claim 34

A direct memory access (DMA) controller for use in a microcomputer system having a central processing unit arranged to execute data processing instructions and produce digital signals, memory for storing a block of data and connected to said central processing unit, and a peripheral device to which the block of data from memory is to be transferred, the DMA controller comprising: a DMA control register; and a DMA control circuit responsive to a first code entered from the system into said DMA control register to start transferring the block, and then upon entry of a second code into the DMA control register during the transfer, to stop the transfer operation within the block in a manner defined by the second code and then start in sequence with a succeeding DMA operation in response to subsequent entry of the first code into the DMA control register.

Claim 35

A direct memory access (DMA) controller for use in a microcomputer system having a central processing unit arranged to execute data processing instructions and produce digital signals, memory for storing a block of data and connected to said central processing unit, and a peripheral device to which the block of data from memory is to be transferred, the DMA controller comprising: a DMA control register; and a DMA control circuit responsive to a first code entered from the system into said DMA control register to start transferring the block, and then upon entry of a second code into the DMA control register during the transfer, to stop the transfer operation within the block in a manner defined by the second code and then start in sequence with a succeeding DMA operation in response to subsequent entry of the first code into the DMA control register.

Claim 36

A DMA controller of claim 30 wherein each of said codes is a two bit code.

Claim 37

A DMA controller of claim 30 wherein each of said codes is a multibit code entered into the same bits of said DMA control register.

Claim 38

A DMA controller of claim 30 wherein said first code is a start code and said second code defines a DMA abort mode.

Claim 39

A DMA controller of claim 30 wherein said second code defines a stop after a current read, whereupon operations start in sequence subsequently with

Claim 40

A DMA controller of claim 30 wherein said second code defines a stop upon reaching a DMA write whereupon operations start in sequence subsequently with a read.

Claim 41

A DMA controller of claim 30 wherein said DMA controller includes means operative during a current DMA read and responsive to a value of the second code defining a stop upon reaching a DMA write for completing the read and executing the write whence stop occurs.

Claim 42

A DMA controller of claim 30 wherein the second code has a first value which defines an unconditional abort of the transfer and a second value alternatively enterable into the DMA control register which defines a stop within the transfer whereupon the transfer is resumed upon entry of the first code.

Claim 45

The method of claim 38 wherein each of said codes is a multibit code entered into the same bits of the DMA control register.

Claim 46

The method of claim 38 wherein said second code can have a plurality of values defining different aborts of the transfer.