Patent US4987470A successfully refreshed from Google Patents.
US4987470A
Expired / Lapsed
US
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Semiconductor dram device having a trench
Assignee: Fujitsu Ltd
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Filing: 1989-01-17
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Granted: 1991-01-22
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Expires: 2009-01-17
Abstract
Abstract A semiconductor device includes a semiconductor substrate having a trench and a transistor region around the trench, the transitor region including source and drain regions and a channel region above which a gate electrode is formed. An insulation film is formed so as to surround sidewalls of the trench. A conductive shield layer is formed along sidewalls of the first insulation film and is located under at least the gate electrode. A memory cell capacitor having first and second electrodes and an insulation film is interposed between the first and second electrodes formed in the trench. The first electrode is electrically connected to the drain region.
Inventors
- 👤 Takaaki Suzuki
- 👤 Hiroshi Gotou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:53
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/05; H10B12/053; H10B12/30; H10B12/34; H10B12/37; H10B12/373; H10B12/39
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
111 words
A semiconductor device having a trench comprising: a semiconductor substrate having a trench and a transistor region surrounded by said trench, said transistor region comprising source and drain regions and a channel region above which a gate electrode is formed; a first insulation film surrounding sidewalls of said trench; a shield layer formed along sidewalls of said first insulation film and located under at least said gate electrode, said shield layer comprising a conductive material; and a memory cell capacitor having first and second electrodes and a second insulation film interposed between said first and second electrodes formed in said trench, said first electrode being electrically connected to said drain region.
Claim 2
Dependent Claim
111 words
A semiconductor device having a trench comprising: a semiconductor substrate having a trench and a transistor region surrounded by said trench, said transistor region comprising source and drain regions and a channel region above which a gate electrode is formed; a first insulation film surrounding sidewalls of said trench; a shield layer formed along sidewalls of said first insulation film and located under at least said gate electrode, said shield layer comprising a conductive material; and a memory cell capacitor having first and second electrodes and a second insulation film interposed between said first and second electrodes formed in said trench, said first electrode being electrically connected to said drain region.
Claim 3
Dependent Claim
19 words
A semiconductor device as claimed in claim 1, wherein said shield layer is electrically connected to said semiconductor substrate.
Claim 4
Dependent Claim
19 words
A semiconductor device as claimed in claim 1, wherein said shield layer is electrically connected to said gate electrode.
Claim 5
Dependent Claim
36 words
A semiconductor device as claimed in claim 1, wherein said shield layer is electrically insulated from said gate electrode, and said first and second electrodes, so that said shield layer is kept in a floating state
Claim 6
Dependent Claim
26 words
A semiconductor device as claimed in claim 2, wherein said shield layer is electrically connected to said semiconductor substrate at a bottom surface of said trench.
Claim 7
Dependent Claim
20 words
A semiconductor device as claimed in claim 5, wherein said shield layer totally overlies the bottom surface of said trench.
Claim 8
Dependent Claim
27 words
A semiconductor device as claimed in claim 1, wherein said shield layer has a U-shaped structure, and is formed so as to partly surround said transistor region.
Claim 9
Dependent Claim
27 words
A semiconductor device as claimed in claim 1, wherein said shield layer comprises two shield layer portions which are arranged along opposite sidewalls of said transistor region.
Claim 10
Dependent Claim
30 words
A semiconductor device as claimed in claim 4, wherein a pulse is applied for every predetermined period across said source region and said second electrode of said memory capacitor cell.
Claim 11
Dependent Claim
14 words
A semiconductor device as claimed in claim 1, wherein said shield layer comprises polysilicon.
Claim 12
Dependent Claim
28 words
A semiconductor device as claimed in claim 10, wherein said shield layer is doped with an impurity of a conductive type identical to that of said semiconductor substrate.
Claim 13
Dependent Claim
21 words
A semiconductor device as claimed in claim 1, wherein said shield layer is approximately 300 Å to approximately 1 μm thick.
Claim 14
Dependent Claim
23 words
A semiconductor device as claimed in claim 1, wherein said transistor region comprises two transistor forming portions, and commonly has the source region.
Claim 15
Dependent Claim
19 words
A semiconductor device as claimed in claim 1, wherein said first and second electrodes are storage and opposed electrodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |