Patent US4987463A successfully refreshed from Google Patents.
US4987463A
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FET having a high trap concentration interface layer
Assignee: Motorola Solutions Inc
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Filing: 1989-08-28
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Granted: 1991-01-22
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Expires: 2009-08-28
Abstract
Abstract A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.
Inventors
- 👤 Herbert Goronkin
- 👤 Saied N. Tehrani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:42
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/50; H10D62/53
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
63 words
A FET having a trap concentrated interface region comprising: a semi-insulating substrate; a trap concentrated interface region having an electrically inactive impurity therein, said region disposed in said substrate; a non-intentionally doped semiconductor buffer layer formed on said trap concentrated interface region of said substrate; a semiconductor layer formed on said buffer layer; and source, gate and drain contacts formed on the FET.
Claim 2
Dependent Claim
63 words
A FET having a trap concentrated interface region comprising: a semi-insulating substrate; a trap concentrated interface region having an electrically inactive impurity therein, said region disposed in said substrate; a non-intentionally doped semiconductor buffer layer formed on said trap concentrated interface region of said substrate; a semiconductor layer formed on said buffer layer; and source, gate and drain contacts formed on the FET.
Claim 3
Dependent Claim
22 words
The FET of claim 1 wherein the semi-insulating substrate comprises one of the group consisting of a III-V compound semiconductor and silicon.
Claim 4
Dependent Claim
19 words
The FET of claim 2 wherein the trap concentrated interface region and the buffer layer comprises the same material.
Claim 5
Dependent Claim
18 words
The FET of claim 3 wherein the trap concentrated interface region and the buffer layer comprise gallium arsenide.
Claim 6
Dependent Claim
19 words
The FET of claim 2 wherein the trap concentrated interface region of the semi-insulating substrate is implanted with oxygen.
Claim 7
Dependent Claim
17 words
The FET of claim 5 wherein the implanted oxygen is in one of blanket and selective form.
Claim 8
Dependent Claim
19 words
The FET of claim 2 wherein the trap concentrated interface region of the semi-insulating substrate is implanted with boron.
Claim 9
Dependent Claim
17 words
The FET of claim 7 wherein the implanted boron is in one of blanket and selective form.
Claim 10
Dependent Claim
73 words
A FET having a trap concentrated interface region comprising: a semi-insulating gallium arsenide substrate; a trap concentrated interface region disposed in said substrate, said trap concentrated interface region being implanted with an electrically inactive impurity; a non-intentionally doped gallium arsenide buffer layer disposed on said trap concentrated interface region of said substrate; a doped aluminum gallium arsenide layer disposed on said buffer layer; and source, gate and drain contacts formed on the FET.
Claim 11
Dependent Claim
73 words
A FET having a trap concentrated interface region comprising: a semi-insulating gallium arsenide substrate; a trap concentrated interface region disposed in said substrate, said trap concentrated interface region being implanted with an electrically inactive impurity; a non-intentionally doped gallium arsenide buffer layer disposed on said trap concentrated interface region of said substrate; a doped aluminum gallium arsenide layer disposed on said buffer layer; and source, gate and drain contacts formed on the FET.
Claim 12
Dependent Claim
23 words
The FET of claim 9 wherein the trap concentrated interface region is implanted with one of the group consisting of oxygen and boron.
Claim 13
Dependent Claim
20 words
The FET of claim 9 wherein the trap concentrated interface region is implanted in one of blanket and selective form.
References Cited (Backward Citations)
US4688062A
Cited
US4745448A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |