Lockproof low level oscillator using digital components

Claim 2

An lockproof oscillator circuit comprising: digital circuit means comprising first, second and third inverters coupled in series and each having an input and an output, the output of said first inverter coupled to the input of said second inverter and the output of said second inverter coupled to the input of said third inverter; said digital circuit being operable between bistable high and low states; a tank circuit comprising capacitance means and an inductance means coupled together to establish a resonant frequency and further coupled to the input of said first inverter; negative feedback means coupled between the output of said third inverter and the input of said first inverter for biasing said digital circuit at an intermediate point between said high and low states; positive feedback means coupled between the output of said second inverter and said tank circuit for delivering energy to said tank circuit and thereby inducing oscillation in said tank circuit at said resonant frequency; said third inverter producing at the output a signal which oscillates between said high and low states in synchronism with the induced oscillation in said tank circuit; said positive feedback means including impedance means for restricting the amount of energy delivered to said tank circuit and thereby reducing the amplitude of said oscillations in said tank circuit without reducing the signal amplitude at the output of said third inverter.

Claim 3

The circuit of claim 1 further comprising frequency selective means associated with said negative feedback means for decoupling said negative feedback means at said resonant frequency.

Claim 4

The circuit of claim 1 wherein said capacitance means comprises series connected capacitors joined at a common node and said positive feedback means is coupled to said common node.

Claim 5

The circuit of claim 1 wherein said impedance means includes a capacitor.

Claim 6

The circuit of claim wherein said impedance means includes a capacitor of substantially greater capacitance than said capacitance means of said tank circuit.

Claim 7

The circuit of claim 5 wherein said capacitor is on the order of 1,000 times the capacitance of said capacitance means.

Claim 8

The circuit of claim 2 wherein said frequency selective means comprises low pass filter means.

Claim 9

The circuit of claim 1 further comprising multiplexing means for selectively coupling said inductance means in said tank circuit.

Claim 10

The circuit of claim 1 further comprising second inductance means and multiplexing means for selectively coupling said inductance means and said second inductance means in said tank circuit.

Claim 11

The circuit of claim 1 further comprising buffer means coupled to the output of said third inverter.

Claim 12

A circuit for measuring inductance of an inductor under test comprising: digital circuit means comprising first, second and third inverters coupled in series and each having an input and an output, the output of said first inverter coupled to the input of said second inverter and the output of said second inverter coupled to the input of said third inverter; said digital circuit being operable between bistable high and low states; a tank circuit comprising a capacitance means and said inductor under test coupled together to establish a resonant frequency and further coupled to the input of said first inverter; negative feedback means coupled between the output of said third inverter and the input of said first inverter for biasing said digital circuit at an intermediate point between said high and low states; positive feedback means coupled between the output of said second inverter and said tank circuit for delivering energy to said tank circuit and thereby inducing oscillation in said tank circuit at said resonant frequency; said third inverter producing at the output a signal which oscillates between said high and low states in synchronism with the induced oscillation in said tank circuit; said positive feedback means including impedance means for restricting the amount of energy delivered to said tank circuit and thereby reducing the amplitude of said oscillations in said tank circuit without reducing the signal amplitude at the output of said third inverter; means for detecting the frequency of said signal at the output of said third inverter to thereby determine the inductance of said inductor under test.

Claim 13

A circuit for measuring inductance of an inductor under test comprising: digital circuit means comprising first, second and third inverters coupled in series and each having an input and an output, the output of said first inverter coupled to the input of said second inverter and the output of said second inverter coupled to the input of said third inverter; said digital circuit being operable between bistable high and low states; a tank circuit comprising a capacitance means and said inductor under test coupled together to establish a resonant frequency and further coupled to the input of said first inverter; negative feedback means coupled between the output of said third inverter and the input of said first inverter for biasing said digital circuit at an intermediate point between said high and low states; positive feedback means coupled between the output of said second inverter and said tank circuit for delivering energy to said tank circuit and thereby inducing oscillation in said tank circuit at said resonant frequency; said third inverter producing at the output a signal which oscillates between said high and low states in synchronism with the induced oscillation in said tank circuit; said positive feedback means including impedance means for restricting the amount of energy delivered to said tank circuit and thereby reducing the amplitude of said oscillations in said tank circuit without reducing the signal amplitude at the output of said third inverter; means for detecting the frequency of said signal at the output of said third inverter to thereby determine the inductance of said inductor under test.

Claim 14

The circuit of claim 11 further comprising frequency selective means associated with said negative feedback means for decoupling said negative feedback means at said resonant frequency.

Claim 15

The circuit of claim 11 wherein said means for detecting the frequency comprises a digital circuit.

Claim 16

The circuit of claim 11 wherein said capacitance means comprises series connected capacitors joined at a common node and said positive feedback means is coupled to said common node.

Claim 17

The circuit of claim 11 wherein said impedance means includes a capacitor.

Claim 18

The circuit of claim 11 wherein said impedance means includes a capacitor of substantially greater capacitance than said capacitance means of said tank circuit.

Claim 19

The circuit of claim 16 wherein said capacitor is on the order of 20 to 1,000 times the capacitance of said capacitance means.

Claim 20

The circuit of claim 12 wherein said frequency selective means comprises low pass filter means.

Claim 21

The circuit of claim 11 further comprising multiplexing means for selectively coupling said inductor under test in said tank circuit.

Claim 22

The circuit of claim 11 further comprising second inductor under test and multiplexing means for selectively coupling said inductor and said second inductor under test in said tank circuit.

Claim 23

The circuit of claim 11 further comprising buffer means coupled to the output of said third inverter.

Claim 24

A multiplexed oscillator circuit comprising: digital circuit means comprising first, second and third inverters coupled in series and each having an input and an output, the output of said first inverter coupled to the input of said second inverter and the output of said second inverter coupled to the input of said third inverter; said digital circuit being operable between bistable high and low states; a first tank circuit comprising a capacitance means and an inductance means coupled together to establish a resonant frequency; a second tank circuit comprising a capacitance means and an inductance means coupled together to establish a resonant frequency; multiplexing means for selectively coupling either said first tank circuit or said second tank circuit to the input of said first inverter; negative feedback means coupled between the output of said third inverter and the input of said first inverter for biasing said digital circuit at an intermediate point between said high and low states; positive feedback means coupled to the output of said second inverter and further coupled to selectively deliver energy to said first and second tank circuits, thereby selectively inducing oscillation in said tank circuits at said resonant frequencies; said third inverter producing at the output at signal which oscillates between said high and low states in synchronism with the induced oscillation in at least one of said tank circuits; said positive feedback means including impedance means for restricting the amount of energy delivered to said tank circuits and thereby reducing the amplitude of said oscillations in said tank circuits without reducing the signal amplitude at the output of said third inverter.

Claim 25

A multiplexed oscillator circuit comprising: digital circuit means comprising first, second and third inverters coupled in series and each having an input and an output, the output of said first inverter coupled to the input of said second inverter and the output of said second inverter coupled to the input of said third inverter; said digital circuit being operable between bistable high and low states; a first tank circuit comprising a capacitance means and an inductance means coupled together to establish a resonant frequency; a second tank circuit comprising a capacitance means and an inductance means coupled together to establish a resonant frequency; multiplexing means for selectively coupling either said first tank circuit or said second tank circuit to the input of said first inverter; negative feedback means coupled between the output of said third inverter and the input of said first inverter for biasing said digital circuit at an intermediate point between said high and low states; positive feedback means coupled to the output of said second inverter and further coupled to selectively deliver energy to said first and second tank circuits, thereby selectively inducing oscillation in said tank circuits at said resonant frequencies; said third inverter producing at the output at signal which oscillates between said high and low states in synchronism with the induced oscillation in at least one of said tank circuits; said positive feedback means including impedance means for restricting the amount of energy delivered to said tank circuits and thereby reducing the amplitude of said oscillations in said tank circuits without reducing the signal amplitude at the output of said third inverter.