Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
286 words
A digital converting apparatus for supplying two trigonometrically related analog signals comprising, a source of clock pulses, a first counter means and a second counter means for counting and registering stepping pulses, a first effective counter including said first counter means, a second effective counter including said second counter means, each of said effective counters having a count range N/2, wherein N is an integer, each of said effective counters being operative to be stepped by stepping pulses derived from said clock pulse source, cyclically through a count range, a reference counter means for establishing a reference point, said reference counter means being operative to be stepped by stepping pulses derived from said clock pulse source, cyclically through a count range of N/2, a digital input in the form of input pulses, generation means, including asymmetry control means, said generation means supplying an equal number of stepping pulses to said first and second effective counters which are equal to the number of stepping pulses supplied to said reference counter means in the absence of said input pulses, said asymmetry control means for supplying an unequal number of stepping pulses to said first and second effective counters in the presence of said input pulse so as to maintain the count difference between said first and second effective counters substantially equally disposed about the count in said reference counter, means for logically combining count registering signals from both said first and second counter means to form two analog signals, each of which is substantially symmetrical about said reference point, said asymmetry control means changing each of said analog signals alternately in magnitude by equal amounts on opposite sides of said reference point in response to successive stepping pulses.
Claim 2
Dependent Claim
286 words
A digital converting apparatus for supplying two trigonometrically related analog signals comprising, a source of clock pulses, a first counter means and a second counter means for counting and registering stepping pulses, a first effective counter including said first counter means, a second effective counter including said second counter means, each of said effective counters having a count range N/2, wherein N is an integer, each of said effective counters being operative to be stepped by stepping pulses derived from said clock pulse source, cyclically through a count range, a reference counter means for establishing a reference point, said reference counter means being operative to be stepped by stepping pulses derived from said clock pulse source, cyclically through a count range of N/2, a digital input in the form of input pulses, generation means, including asymmetry control means, said generation means supplying an equal number of stepping pulses to said first and second effective counters which are equal to the number of stepping pulses supplied to said reference counter means in the absence of said input pulses, said asymmetry control means for supplying an unequal number of stepping pulses to said first and second effective counters in the presence of said input pulse so as to maintain the count difference between said first and second effective counters substantially equally disposed about the count in said reference counter, means for logically combining count registering signals from both said first and second counter means to form two analog signals, each of which is substantially symmetrical about said reference point, said asymmetry control means changing each of said analog signals alternately in magnitude by equal amounts on opposite sides of said reference point in response to successive stepping pulses.
Claim 3
Dependent Claim
106 words
The apparatus of claim 1 further including a binary state directional store for storing a direction signal which indicates the positive or negative count direction for each of said input pulses and wherein said asymmetry control means includes alternating means, said alternating means being changed in state in the absence of a change in said direction signal, for each of said input pulses, means for detecting a change in state of said direction signal for two successive input pulses, said means for detecting being operative, when energized, to inhibit the change in state of said alternating means on the second of said two successive input pulses.
Claim 4
Dependent Claim
49 words
The apparatus of claim 2 wherein for said direction signal at a first state, said first and second effective counters are stepped with 0 and 1 pulse, respectively, by said asymmetry control means and with 1 and 2 pulses, respectively, by said asymmetry control means with alternate input pulses.
Claim 5
Dependent Claim
39 words
The apparatus of claim 3 wherein for said direction signal at a second state, said first and second effective counters are stepped with 1 and 0 pulse, respectively, and with 2 and 1 pulses, respectively, with alternate input pulses.
Claim 6
Dependent Claim
81 words
The apparatus of claim 4 wherein a change in state of said direction signal causes said counters when counting in the 0 and 1 mode or in the 1 and 0 mode to count for the next input pulse in the 2 and 1 or 1 and 2 mode, respectively, or when counting in the 1 and 2 or 2 and 1 mode to count for the next input pulse in the 1 and 0 or 0 and 1 mode, respectively.
Claim 7
Dependent Claim
270 words
A digital converting apparatus comprising, a source of clock pulses of frequency NE/2 wherein N is an integer and F is a fundamental frequency, first counter means and second counter means each operative to be stepped by stepping pulsEs cyclically through a count range N/4, a digital input including input pulses, generation means for generating a digital count representing a digital magnitude where n is equal to the algebraically accumulated difference in count between the numbers of input pulses registered in said first and second counter means, said generation means including asymmetry control means having, first and second digital dividers connected in combination with said first and second counter means, respectively, to form first and second effective counters, respectively, each of count range N/2, a reference counter means for establishing a reference point, said reference counter means being operative to be stepped by stepping pulses derived from said clock pulse source, cyclically through a count range of N/2, means for providing unequal numbers of stepping pulses to said first and second effective counters to produce said count difference n where the difference in said numbers equals 1 for each of said input pulses, means for logically combining signals from both said first and second counter means so as to generate first and second output signals each including an analog component, at said fundamental frequency, F, proportional to a trigonometric function of an angle theta where theta equals (n/N)360* and where said first and second output signals are changed in width by said asymmetry control means, said change in width being produced alternately at opposite ends thereof about said reference point.
Claim 8
Dependent Claim
270 words
A digital converting apparatus comprising, a source of clock pulses of frequency NE/2 wherein N is an integer and F is a fundamental frequency, first counter means and second counter means each operative to be stepped by stepping pulsEs cyclically through a count range N/4, a digital input including input pulses, generation means for generating a digital count representing a digital magnitude where n is equal to the algebraically accumulated difference in count between the numbers of input pulses registered in said first and second counter means, said generation means including asymmetry control means having, first and second digital dividers connected in combination with said first and second counter means, respectively, to form first and second effective counters, respectively, each of count range N/2, a reference counter means for establishing a reference point, said reference counter means being operative to be stepped by stepping pulses derived from said clock pulse source, cyclically through a count range of N/2, means for providing unequal numbers of stepping pulses to said first and second effective counters to produce said count difference n where the difference in said numbers equals 1 for each of said input pulses, means for logically combining signals from both said first and second counter means so as to generate first and second output signals each including an analog component, at said fundamental frequency, F, proportional to a trigonometric function of an angle theta where theta equals (n/N)360* and where said first and second output signals are changed in width by said asymmetry control means, said change in width being produced alternately at opposite ends thereof about said reference point.
Claim 9
Dependent Claim
106 words
The apparatus of claim 6 further including a binary state directional store for storing a direction signal which indicates the positive or negative count direction for each of said input pulses and wherein said asymmetry control means includes alternating means, said alternating means being changed in state, in the absence of a change in said direction signal, for each of said input pulses, means for detecting a change in state of said direction signal for two successive input pulses, said means for detecting being operative, when energized, to inhibit the change in state of said alternating means on the second of said two successive input pulses.
Claim 10
Dependent Claim
49 words
The apparatus of claim 7 wherein for said direction signal at a first state, said first and second effective counters are stepped with 0 and 1 pulse, respectively, by said asymmetry control means and with 1 and 2 pulses, respectively, by said asymmetry control means with alternate input pulses.
Claim 11
Dependent Claim
39 words
The apparatus of claim 8 wherein for said direction signal at a second state, said first and second effective counters are stepped with 1 and 0 pulse, respectively, and with 2 and 1 pulses, respectively, with alternate input pulses.
Claim 12
Dependent Claim
81 words
The apparatus of claim 8 wherein a change in state of said direction signal causes said counter when counting in the 0 and 1 mode or in the 1 and 0 mode to count for the next input pulse in the 2 and 1 or 1 and 2 mode, respectively, or when counting in the 1 and 2 or 2 and 1 mode to count for the next input pulse in the 1 and 0 or 0 and 1 mode, respectively.