SIMD array processing system with routing networks having plurality of switching stages to transfer messages among processors

Claim 2

A routing network for transferring messages, each message including an address and data, among a plurality of processing elements in an array processing system, said routing network comprising: I. a series of initial switching stages each including: A. a plurality of switching elements, each comprising a plurality of output terminal groups, each group comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means, wherein all of said data lines, from each said switching element in said switching stage, connected to said output terminal means belonging to said output terminal group identified by the same said address decoding, are also connected to the same switching element in the next switching stage; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from the address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means; and II. a crossbar switch stages for receiving messages from the output terminal groups of the last of the series of initial switching stages, for performing a switching operation in connection with the messages, and for coupling the switched messages to the processing elements.

Claim 3

A routing network as defined in claim 1 in which the coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line.

Claim 4

A routing network as defined in claim 2 in which each output terminal means includes means for generating a coupling enabling signal in response to a selected condition, each coupling means including: A. coupling enabling signal receiving means for receiving a coupling enabling signal; B. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal for coupling data from said input circuit means onto a data line; and C. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling means does not couple data from said input circuit means onto a data line.

Claim 5

A routing network as defined in claim 3 in which said data coupling means comprises: A. pass transistor means connected to said input circuit means and said data line for transferring data between said input circuit means, data output terminal and said data line in response to a pass transistor control signal; B. control signal generating means connected to receive said coupling enabling signal and said address enabling signal for generating said pass transistor control signal in response to the coincidence of said address enabling signal and said coupling enabling signal.

Claim 6

A routing network as defined in claim 4 in which said coupling means further includes coincidence means connected to receive said coupling enabling signal and said address enabling signal for transmitting an address enabling signal to said next lower order coupling means in response to the coincidence of the assertion of said address enabling signal and the negation of said coupling enabling signal.

Claim 7

A routing network as defined in claim 1 in which said input circuit means further includes block signal generating means for generating a block signal in response to a selected condition, said address control circuits being disabled in response to the receipt of a block signal.

Claim 8

A routing network as defined in claim 6 in which each said address control circuit includes: A. block signal receiving means connected to said input circuit means for receiving said block signal; B. address decoding means connected to said input circuit means for generating an address decode signal in response to a selected decoding of the address from said input circuit means; C. address enabling signal generating means connected to said block signal receiving means and said address decoding means for generating said address enabling signal in response to the receipt of said address decode signal and the absence of said block signal.

Claim 9

A routing network as defined in claim 6 in which said address includes a protocol bit, said input circuit including protocol means for detecting said protocol bit and for generating a mess signal if said protocol bit is not detected, said block signal generating means being connected to said protocol means for generating said block signal in response to the generation of said miss signal.

Claim 10

A routing network as defined in claim 6 in which said each input circuit means is connected to a message transfer wire for receiving a message thereover, said input circuit including broken wire detection means for detecting the condition of the message transfer wire and generating a broken wire signal in response thereto, said block signal generating means being connected to said broken wire detection means for generating said block signal in response to the generation of said broken wire signal.

Claim 11

A routing network as defined in claim 9 in which each said output terminal means is also connected to a message transfer wire, said message transfer wire transferring messages between said output terminal means of one of said initial switching stages and said input means of succeeding one of said initial switching stages, said output terminal means also including broken wire detection means, A. each said broken wire detection means including: i. broken wire signal generating means connected to said message transfer wire for transmitting a signal over said message transfer wire; ii. broken wire latch means connected to said message transfer wire for latching a signal received over said message transfer wire and generate said broken wire signal in response to the condition of the latched signal; and B. said routing network further including broken wire control means connected to said broken wire signal generating means and said broken wire latch means in each broken wire detection means for separately enabling said broken wire generating means in said input means and said output terminal means to transmit a signal on the message transfer line, and the broken wire latch means in the other of input means and said output terminal means to latch the condition of the signal on the message transfer line.

Claim 12

A routing network as defined in claim 1 in which said address comprises a predetermined number of serial address bit signals, and wherein said address control circuits in each circuit means are connected in series ordered relationship from the circuit means' input circuit means, each address control circuit including: A. address bit signal receiving means for receiving an address bit signal from said input circuit or from another address control circuit in said series order; B. address bit complement means connected to said address bit signal receiving means for generating a complement address bit signal in response to the address bit signal received by said address bit signal receiving means; C. multiplexer means connected to said address bit signal receiving means and said address bit complement means for selectively coupling either the address bit signal or the complement address bit signal to the next address control circuit in the series order; and D. control means connected to said address bit signal receiving means and said multiplexer means for controlling said multiplexer means, said control means including: i. address bit signal coupling means connected to said address bit signal receiving means for coupling said address bit signal received by said address bit signal receiving means; ii. latch means connected to said address bit signal coupling means and said multiplexer means for latching the address bit signal received from said address bit signal coupling means and for controlling said address bit signal coupling means and said multiplexer means in response thereto, said latch means controlling said address bit signal coupling means to couple address bit signals thereto while said address bit signals have a selected condition and contemporaneously enabling said multiplexer means to couple the complement address bit signal to the next address control circuit, and to disable said address bit signal coupling means on receipt of an address bit signal having another condition and contemporaneously enabling said multiplexer means to couples said address bit signal to the next address control circuit.

Claim 13

A routing network as defined in claim 1 for transferring messages each including an acknowledge bit in response to an acknowledge transfer enabling signal, each output terminal means includes means connected to its data line and an output terminal for coupling data signals from said data line to said output terminal, and output gate means connected to said output terminal and said data line for coupling said acknowledge bit from said output terminal to said data line in response to said acknowledge transfer enabling signal, each of said input circuit means including input gate means connected to said data output terminal and for coupling said acknowledge bit from said data output terminal to said input terminal in response to the receipt of said acknowledge transfer enabling signal.

Claim 14

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of switching elements, each comprising a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means, wherein all said data lines, from each said switching element in said switching stage, connected to said output terminal means belonging to said output terminal group identified by the same said address decoding, are also connected to same said switching element in the next subsequent routing stage; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuit for decoding the address from address output terminal of said input circuit means each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 15

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of switching elements, each comprising a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means, wherein all said data lines, from each said switching element in said switching stage, connected to said output terminal means belonging to said output terminal group identified by the same said address decoding, are also connected to same said switching element in the next subsequent routing stage; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuit for decoding the address from address output terminal of said input circuit means each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 16

A routing network as defined in claim 13 in which the coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line.

Claim 17

A routing stage as defined in claim 14 in which each output terminal means includes means for generating a coupling enabling signal in response to a selected condition, each coupling means including: A. coupling enabling signal receiving means for receiving a coupling enabling signal; B. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal for coupling data from said input circuit means onto a data line; and C. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling means does not couple data from said input circuit means onto a data line.

Claim 18

A routing network as defined in claim 15 in which said data coupling means comprises: A. pass transistor means connected to said input circuit means and said data line for transferring data between said input circuit means' data output terminal and said data line in response to a pass transistor control signal; B. control signal generating means connected to receive said coupling enabling signal and said address enabling signal for generating said pass transistor control signal in response to the coincidence of said address enabling signal and said coupling enabling signal.

Claim 19

A routing network as defined in claim 16 in which said coupling means further includes coincidence means connected to receive said coupling enabling signal and said address enabling signal for transmitting an address enabling signal to said next lower order coupling means in response to the coincidence of an assertion of said address enabling signal and the negation of said coupling enabling signal.

Claim 20

A routing stage as defined in claim 13 in which said input circuit means further includes block signal generating means for generating a block signal in response to a selected condition, said address control circuit being disabled in response to the receipt of a block signal.

Claim 21

A routing stage as defined in claim 18 in which each said address control circuit includes: A. block signal receiving means connected to said input circuit means for receiving said block signal; B. address decoding means connected to said input circuit means for generating an address decode signal in response to a selected decoding of the address from said input circuit means; C. address enabling signal generating means connected to said block signal receiving means and said address decoding means for generating said address enabling signal in response to the receipt of said address decode signal and the absence of said block signal.

Claim 22

A routing stage as defined in claim 18 in which said address includes a protocol bit, said input circuit including protocol means for detecting said protocol bit and for generating a miss signal if said protocol bit it not detected, said block signal generating means being connected to said protocol means for generating said block signal in response to the generation of said miss signal.

Claim 23

A routing stage as defined in claim 18 in which said each input circuit means is connected to a message transfer wire for receiving a message thereover, said input circuit including broken wire detection means for detecting the condition of the message transfer wire and generating a broken wire signal in response thereto, said block signal generating means being connected to said broken wire detection means for generating said block signal in response to the generation of said broken wire signal.

Claim 24

A routing stage as defined in claim 21 in which each said output terminal means is also connected to a message transfer wire, said message transfer wires transferring messages between said output terminal means and said input means, said output terminal means also including broken wire detection means, A. each said broken wire detection means including: i. broken wire signal generating means connected to said message transfer wire for transmitting a signal over said message transfer wire; ii. broken wire latch means connected to said message transfer wire for latching a signal received over said message transfer wire and generate said broken wire signal in response to the condition of the latched signal; and B. said routing network further including broken wire control means connected to said broken wire signal generating means and said broken wire latch means in each broken wire detection means for separately enabling said broken wire signal generating means in said input means and said output terminal means to transmit a signal on the message transfer line, and the broken wire latch means in the other of input means and said output terminal means to latch the condition of the signal on the message transfer line.

Claim 25

A routing stage as defined in claim 13 in which said address comprises a predetermined number of serial address bit signals, and wherein said address control circuits in each circuit means are connected in series ordered relationship for the circuit means' input circuit means, each address control circuit including: A. address bit signal receiving means for receiving an address bit signal from said input circuit or from another address control circuit in said series order; B. address bit complement means connected to said address bit signal receiving means for generating a complement address bit signal in response to the address bit signal received by said address bit signal receiving means; C. multiplexer means connected to said address bit signal receiving means and said address bit complement means for selectively coupling either the address bit signal or the complement address bit signal to the next address control circuit in the series order; and D. control means connected to said address bit signal receiving means and said multiplexer means for controlling said multiplexer means, said control means including: i. address bit signal coupling means connected to said address bit signal receiving means for coupling said address bit signal received by said address bit signal receiving means; ii. latch means connected to said address bit signal coupling means and said multiplexer means for latching the address bit signal received from said address bit signal coupling means and for controlling said address bit signal coupling means and said multiplexer means in response thereto, said latch means controlling said address bit signal coupling means to couple address bit signals thereto while said address bit signals have a selected condition and contemporaneously enabling said multiplexer means to couple the complement address bit signal to the next address control circuit, and to disable said address bit signal coupling means on receipt of an address bit signal having another condition and contemporaneously enabling said multiplexer means to couples said address bit signal to the next address control circuit.

Claim 26

A routing stage as defined in claim 13 for transferring messages each including an acknowledge bit in response to an acknowledge transfer enabling signal, each output terminal means includes means connected to its data line and an output terminal for coupling data signals from said data line to said output terminal, and output gate means connected to said output terminal and said data line for coupling said acknowledge bit from said output terminal to said data line in response to said acknowledge transfer enabling signal, each of said input circuit means including input gate means connected to said data output terminal and for coupling said acknowledge bit from said data output terminal to said input terminal in response to the receipt of said acknowledge transfer enabling signal.

Claim 27

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line, each coupling means including: a. coupling enabling signal receiving means for receiving a coupling enabling signal; b. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal for coupling data from said input circuit means onto a data line; and c. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling mean does not couple data from said input circuit means on to a data line.

Claim 28

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line, each coupling means including: a. coupling enabling signal receiving means for receiving a coupling enabling signal; b. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal for coupling data from said input circuit means onto a data line; and c. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling mean does not couple data from said input circuit means on to a data line.

Claim 29

A routing network as defined in claim 25 in which said data coupling means comprises: A. pass transistor means connected to said input circuit means and said data line for transferring data between said input circuit means' data output terminal and said data line in response to a pass transistor control signal; B. control signal generating means connected to receive said coupling enabling signal and said address enabling signal for generating said pass transistor control signal in response to the coincidence of said address enabling signal and said coupling enabling signal.

Claim 30

A routing network as defined in claim 26 in which said coupling means further includes coincidence means connected to receive said coupling enabling signal and said address enabling signal for transmitting an address enabling signal to said next lower order coupling means in response to the coincidence of the assertion of said address enabling signal and the negation of said coupling enabling signal.

Claim 31

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, said address including a protocol bit, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data, said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. protocol means for detecting said protocol bit and for generating a miss signal if said protocol bit is not detected, said block signal generating means being connected to said protocol means for generating said block signal in response to the generation of said miss signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, said address control circuits being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 32

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, said address including a protocol bit, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data, said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. protocol means for detecting said protocol bit and for generating a miss signal if said protocol bit is not detected, said block signal generating means being connected to said protocol means for generating said block signal in response to the generation of said miss signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, said address control circuits being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 33

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data, said each input circuit means is connected to a message transfer wire for receiving a message thereover, said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. broken wire detection means for detecting the condition of the message transfer wire and generating a broken wire signal is response thereto, said block signal generating means being connected to said broken wire detection means for generating said block signal in response to the generation of said broken wire signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, said address control circuit being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 34

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data, said each input circuit means is connected to a message transfer wire for receiving a message thereover, said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. broken wire detection means for detecting the condition of the message transfer wire and generating a broken wire signal is response thereto, said block signal generating means being connected to said broken wire detection means for generating said block signal in response to the generation of said broken wire signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, said address control circuit being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 35

A routing network as defined in claim 29 in which each said output terminal means is also connected to a message transfer wire, said message transfer wires transferring messages between said output terminal means of one of said initial switching stages and said input means of succeeding one of said initial switching stages, said output terminal means also including broken wire detection means, A. each said broken wire detection means including: i. broken wire signal generating means connected to said message transfer wire for transmitting a signal over said message transfer wire; ii. broken wire latch means connected to said message transfer wire for latching a signal received over said message transfer wire and generate said broken wire signal in response to the condition of the latched signal; and B. said routing network further including broken wire control means connected to said broken wire signal generating means and said broken wire latch means in each broken wire detection means for separately enabling said broken wire generating means in said input means and said output terminal means to transmit a signal on the message transfer line, and the broken wire latch means in the other of input means and said output terminal means to latch the condition of the signal on the message transfer line.

Claim 36

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input messages and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, wherein said address comprises a predetermined number of serial address bit signals, and wherein said address control circuits in each circuit means are connected in series ordered relationship from the circuit means' input circuit means, each address control circuit including: a. address bit signal receiving means for receiving an address bit signal from said input circuit or from another address control circuit in said series order; b. address bit signal complement means connected to said address bit signal receiving means for generating a complement address bit signal in response to the address bit signal received by said address bit signal receiving means; c. multiplexer means connected to said address bit signal receiving means and said address bit complement means for selectively coupling either the address bit signal or the complement address bit signal to the next address control circuit in the series order; and d. control means connected to said address bit signal receiving means and said multiplexer means for controlling said multiplexer means, said control means including: (i.) address bit signal coupling means connected to said address bit signal receiving means for coupling said address bit signal received by said address bit signal receiving means; (ii.) latch means connected to said address bit signal coupling means and said multiplexer means for latching the address bit signal received from said address bit signal coupling means and for controlling said address bit signal coupling means and said multiplexer means in response thereto, said latch means controlling said address bit signal coupling means to couple address bit signals thereto while said address bit signals have a selected condition and contemporaneously enabling said multiplexer means to couple the complement address bit signal to the next address control circuit, and to disable said address bit signal coupling means on receipt of an address bit signal having another condition and contemporaneously enabling said multiplexer means to couple said address bit signal to the next address control circuit; (iii.) a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 37

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input messages and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, wherein said address comprises a predetermined number of serial address bit signals, and wherein said address control circuits in each circuit means are connected in series ordered relationship from the circuit means' input circuit means, each address control circuit including: a. address bit signal receiving means for receiving an address bit signal from said input circuit or from another address control circuit in said series order; b. address bit signal complement means connected to said address bit signal receiving means for generating a complement address bit signal in response to the address bit signal received by said address bit signal receiving means; c. multiplexer means connected to said address bit signal receiving means and said address bit complement means for selectively coupling either the address bit signal or the complement address bit signal to the next address control circuit in the series order; and d. control means connected to said address bit signal receiving means and said multiplexer means for controlling said multiplexer means, said control means including: (i.) address bit signal coupling means connected to said address bit signal receiving means for coupling said address bit signal received by said address bit signal receiving means; (ii.) latch means connected to said address bit signal coupling means and said multiplexer means for latching the address bit signal received from said address bit signal coupling means and for controlling said address bit signal coupling means and said multiplexer means in response thereto, said latch means controlling said address bit signal coupling means to couple address bit signals thereto while said address bit signals have a selected condition and contemporaneously enabling said multiplexer means to couple the complement address bit signal to the next address control circuit, and to disable said address bit signal coupling means on receipt of an address bit signal having another condition and contemporaneously enabling said multiplexer means to couple said address bit signal to the next address control circuit; (iii.) a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 38

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising aplurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means; wherein each said message includes an acknowledge bit in response to an acknowledge transfer enabling signal, each output terminal means includes means connected to its data line and an output terminal for coupling data signals from said data line to said output terminal, and output gate means connected to said output terminal and said data line for coupling said acknowledge bit from said output terminal to said data line in response to said acknowledge transfer enabling signal, each of said input circuit means including input gate means connected to said data output terminal and for coupling said acknowledge bit from said data output terminal to said input terminal in response to the receipt of said acknowledge transfer enabling signal.

Claim 39

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising aplurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means; wherein each said message includes an acknowledge bit in response to an acknowledge transfer enabling signal, each output terminal means includes means connected to its data line and an output terminal for coupling data signals from said data line to said output terminal, and output gate means connected to said output terminal and said data line for coupling said acknowledge bit from said output terminal to said data line in response to said acknowledge transfer enabling signal, each of said input circuit means including input gate means connected to said data output terminal and for coupling said acknowledge bit from said data output terminal to said input terminal in response to the receipt of said acknowledge transfer enabling signal.

Claim 40

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. A plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected to a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line, each coupling means including: a. coupling enabling signal receiving means for receiving a coupling enabling signal; b. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal for coupling data from said input circuit means onto a data line, said data coupling means comprises: (i.) pass transistor means connected to said input circuit means and said data line for transferring data between said input circuit menas' data output terminal and said data line in response to a pass transistor control signal; (ii.) control signal generating means connected to receive said coupling enabling signal and said address enabling signal for generating said pass transistor control signal in response to the coincidence of said address enabling signal and said coupling enabling signal; c. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling means does not couple data from said input circuit means onto a data line.

Claim 41

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. A plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected to a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line, each coupling means including: a. coupling enabling signal receiving means for receiving a coupling enabling signal; b. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal for coupling data from said input circuit means onto a data line, said data coupling means comprises: (i.) pass transistor means connected to said input circuit means and said data line for transferring data between said input circuit menas' data output terminal and said data line in response to a pass transistor control signal; (ii.) control signal generating means connected to receive said coupling enabling signal and said address enabling signal for generating said pass transistor control signal in response to the coincidence of said address enabling signal and said coupling enabling signal; c. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling means does not couple data from said input circuit means onto a data line.

Claim 42

A routing network as defined in claim 33 in which said coupling means further includes coincidence means connected to receive said coupling enabling signal and said address enabling signal for transmitting an address enabling signal to said next lower order coupling means in response to the coincidence of an assertion of said address enabling signal and the negation of said coupling enabling signal.

Claim 43

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, said address including a protocol bit; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. a protocol means for detecting said protocol bit and for generating a miss signal if said protocol bit it not detected, said block signal generating means being connected to said protocol means for generating said block signal in response to the generation of said miss signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address said address control circuit being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 44

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, said address including a protocol bit; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. a protocol means for detecting said protocol bit and for generating a miss signal if said protocol bit it not detected, said block signal generating means being connected to said protocol means for generating said block signal in response to the generation of said miss signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address said address control circuit being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 45

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of a data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data said each input circuit means is connected to a message transfer wire for receiving a message thereover, said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. broken wire detection means for detecting the condition of the message transfer wire and generating a broken wire signal in response thereto, said block signal generating means being connected to said broken wire detection means for generating said block signal in response to the generation of said broken wire signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, said address control circuit being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 46

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of a data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data said each input circuit means is connected to a message transfer wire for receiving a message thereover, said input circuit means further includes: a. block signal generating means for generating a block signal in response to a selected condition; b. broken wire detection means for detecting the condition of the message transfer wire and generating a broken wire signal in response thereto, said block signal generating means being connected to said broken wire detection means for generating said block signal in response to the generation of said broken wire signal; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, said address control circuit being disabled in response to the receipt of a block signal; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 47

A routing stage as defined in claim 36 in which each said output terminal means is also connected to a message transfer wire, said message transfer wires transferring messages between said output terminal means and said input means, said output terminal means also including broken wire detection means, A. each said broken wire detection means including: i. broken wire signal generating means connected to said message transfer wire for transmitting a signal over said message transfer wire; ii. broken wire latch means connected to said message transfer wire for latching a signal received over said message transfer wire and generate said broken wire signal in response to the condition of the latched signal; and B. said routing network further including broken wire control means connected to said broken wire signal generating means and said broken wire latch means in reach broken wire detection means for separately enabling said broken wire signal generating means in said input means and said output terminal means to transmit a signal on the message transfer line, and the broken wire latch means in the other of input means and said output terminal means to latch the condition of the signal on the message transfer line.

Claim 48

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, wherein said address comprises a predetermined number of serial address bit signals, and wherein said address control circuits in each circuit means are connected in series ordered relationship form the circuit means' input circuit means, each address control circuit including: a. address bit signal receiving means for receiving an address bit signal from said input circuit or from another address control circuit in said series order; b. address bit signal complement means connected to said address bit signal receiving means for generating a complement address bit signal in response to the address bit signal received by said address bit signal receiving means; c. multiplexer means connected to said address bit signal receiving means and said address bit complement means for selectively coupling either the address bit signal or the complement address bit signal to the next address control circuit in the series order; and d. control means connected to said address bit signal receiving means and said multiplexer means for controlling said multiplexer means, said control means including: (i.) address bit signal coupling means connected to said address bit signal receiving means for coupling said address bit signal received by said address bit signal receiving means; (ii.) latch means connected to said address bit signal coupling means and said multiplexer means for latching the address bit signal received from said address bit signal coupling means and for controlling said address bit signal coupling means and said multiplexer means in response thereto, said latch means controlling said address bit signal coupling means to couple address bit signals thereto while said address bit signals have a selected condition and contemporaneously enabling said multiplexer means to couple the complement address bit signal to the next address control circuit, and to disable said address bit signal coupling means on receipt of an address bit signal having another condition and contemporaneously enabling said multiplexer means to couple said address bit signal to the enxt address control circuit; (iii.) a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 49

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address, wherein said address comprises a predetermined number of serial address bit signals, and wherein said address control circuits in each circuit means are connected in series ordered relationship form the circuit means' input circuit means, each address control circuit including: a. address bit signal receiving means for receiving an address bit signal from said input circuit or from another address control circuit in said series order; b. address bit signal complement means connected to said address bit signal receiving means for generating a complement address bit signal in response to the address bit signal received by said address bit signal receiving means; c. multiplexer means connected to said address bit signal receiving means and said address bit complement means for selectively coupling either the address bit signal or the complement address bit signal to the next address control circuit in the series order; and d. control means connected to said address bit signal receiving means and said multiplexer means for controlling said multiplexer means, said control means including: (i.) address bit signal coupling means connected to said address bit signal receiving means for coupling said address bit signal received by said address bit signal receiving means; (ii.) latch means connected to said address bit signal coupling means and said multiplexer means for latching the address bit signal received from said address bit signal coupling means and for controlling said address bit signal coupling means and said multiplexer means in response thereto, said latch means controlling said address bit signal coupling means to couple address bit signals thereto while said address bit signals have a selected condition and contemporaneously enabling said multiplexer means to couple the complement address bit signal to the next address control circuit, and to disable said address bit signal coupling means on receipt of an address bit signal having another condition and contemporaneously enabling said multiplexer means to couple said address bit signal to the enxt address control circuit; (iii.) a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means.

Claim 50

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means; wherein each said message includes an acknowledge bit in response to an acknowledge transfer enabling signal, each output terminal means includes means connected to its data line and an output terminal for coupling data signals from said data line to said output terminal, and output gate means connected to said output terminal and said data line for coupling said acknowledge bit from said output terminal to said data line in response to said acknowledge transfer enabling signal, each of said input circuit means including input gate means connected to said data output terminal and for coupling said acknowledge bit from said data output terminal to said input terminal in response to the receipt of said acknowledge transfer enabling signal.

Claim 51

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means; wherein each said message includes an acknowledge bit in response to an acknowledge transfer enabling signal, each output terminal means includes means connected to its data line and an output terminal for coupling data signals from said data line to said output terminal, and output gate means connected to said output terminal and said data line for coupling said acknowledge bit from said output terminal to said data line in response to said acknowledge transfer enabling signal, each of said input circuit means including input gate means connected to said data output terminal and for coupling said acknowledge bit from said data output terminal to said input terminal in response to the receipt of said acknowledge transfer enabling signal.

Claim 52

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to received said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line, each coupling means including: a. coupling enabling signal receiving means for receiving a coupling enabling signal; b. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal from coupling data from said input circuit means onto a data line; and c. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling means does not couple data from said input circuit means onto a data line.

Claim 53

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to received said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line, each coupling means including: a. coupling enabling signal receiving means for receiving a coupling enabling signal; b. data coupling means responsive to the receipt of a coupling enabling signal and an address enabling signal from coupling data from said input circuit means onto a data line; and c. coupling enabling signal transmitting means connected to said coupling enabling signal receiving means and said data coupling means for transmitting the coupling enabling signal to another coupling means in response to the receipt of a coupling enabling signal if said data coupling means does not couple data from said input circuit means onto a data line.

Claim 54

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data rom said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line.

Claim 55

A routing network for transferring messages among a plurality of processing elements in an array processing system, said routing network switching messages in a plurality of initial switching stages and terminating in a crossbar switch stage, each processing element transmitting an address and data with each message, each of said initial switching stages including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data rom said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line.

Claim 56

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line.

Claim 57

A routing stage for transferring messages among a plurality of processing elements in a routing network, the routing stage including: A. a plurality of output terminal groups each comprising a plurality of output terminal means, each output terminal group being identified by a decoding of a selected portion of an address, and each output terminal means includes means for generating a coupling enabling signal in response to a selected condition; B. a plurality of data lines each connected to an output terminal means; C. circuit means for receiving a message and coupling it onto a selected one of said data lines, said circuit means including: i. input circuit means for receiving an input message and having an address output terminal for transmitting said address and a data output terminal for transmitting said data; ii. a plurality of address control circuits for decoding the address from address output terminal of said input circuit means, each address control circuit generating an address enabling signal in response to a predetermined encoding of the address; and iii. a plurality of coupling means groups each connected to an address control circuit for receiving an enabling signal therefrom, each coupling means group including a plurality of coupling means each connected to a data line, one of said coupling means within a coupling means group coupling said data from said input circuit means onto a data line in response to the receipt of said address enabling signal from said address circuit means, wherein said coupling means within said coupling means group are interconnected in a predetermined order, with a high order coupling means being connected to receive said address enabling signal from said address control circuit, and each coupling means being connected to transmit the address enabling signal to the next lower order coupling means if it does not couple said data from said input circuit means onto a data line.