US3727006A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-stage time connection network
Assignee: Nokia Inc
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Filing: 1971-02-10
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Granted: 1973-04-10
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Expires: 1991-02-10
Abstract
Abstract Test device comprising a central memory storing a record of the engaged states of the paths in a multi-stage switching network, consisting more particularly of a single memory block for two connection networks whose intermediate switches can receive data from the input switches of any of the networks, whereas they can transmit the said data only to the output switches of the network to which they belong.
Inventors
- 👤 J Jacob
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:05
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q11/00; H04Q11/04; H04Q11/08; H04Q3/52
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
288 words
A path finding system for a time division multiplex communication network for providing switching paths for time division multiplex signals transmitted therethrough, comprising: first and second identical multi-stage connection networks, each including an input stage, an intermediate stage, and an output stage, the input stage of each connection network comprising p input time switches having n incoming and m outgoing network lines, the intermediate stage of each connection network comprising m intermediate time switches with two p inputs and q outputs, and the output stage of each connection network comprising q output switches with m inputs and n outgoing network lines, each network line including a plurality of time channels and the switches having the same internal time division switching arrangement, each input time switch of one network being connected to respective inputs of the intermediate time switches of that network and to respective inputs of the intermediate time switches of the other network, each intermediate time switch being connected by means of an intermediate network line with the respective inputs of the output time switches of the network; central memory means, coupled to the intermediate stages of said first and second connection networks, for storing the busy or free condition of all the time channels of the incoming and outgoing network lines of each time switch in said intermediate stages; and access means, coupled between said central memory means and said intermediate stages, for reading into said memory means the condition of each intermediate time switch and for writing in each intermediate time switch the busy or free condition of each time channel in the incoming and outgoing network lines; and wherein said central memory means includes individual memory portions for said first and second connection networks.
Claim 2
Dependent Claim
288 words
A path finding system for a time division multiplex communication network for providing switching paths for time division multiplex signals transmitted therethrough, comprising: first and second identical multi-stage connection networks, each including an input stage, an intermediate stage, and an output stage, the input stage of each connection network comprising p input time switches having n incoming and m outgoing network lines, the intermediate stage of each connection network comprising m intermediate time switches with two p inputs and q outputs, and the output stage of each connection network comprising q output switches with m inputs and n outgoing network lines, each network line including a plurality of time channels and the switches having the same internal time division switching arrangement, each input time switch of one network being connected to respective inputs of the intermediate time switches of that network and to respective inputs of the intermediate time switches of the other network, each intermediate time switch being connected by means of an intermediate network line with the respective inputs of the output time switches of the network; central memory means, coupled to the intermediate stages of said first and second connection networks, for storing the busy or free condition of all the time channels of the incoming and outgoing network lines of each time switch in said intermediate stages; and access means, coupled between said central memory means and said intermediate stages, for reading into said memory means the condition of each intermediate time switch and for writing in each intermediate time switch the busy or free condition of each time channel in the incoming and outgoing network lines; and wherein said central memory means includes individual memory portions for said first and second connection networks.
Claim 3
Dependent Claim
65 words
Device according to claim 1, wherein said central memory means for the information concerning the states of occupancy of the network includes a block memory comprising 2 (p X m) words of 32 binary elements corresponding to the outgoing network lines of the input time switches, and 2m X q words of 32 binary elements corresponding to the outgoing lines of the intermediate time switches.
Claim 4
Dependent Claim
114 words
Device according to claim 2, wherein said acess means includes register means for controlling the addressing of said block memory, the storage location for each word of said block memory being operatively associated with an input gate having several inputs, and characterized in that each of said input gates comprise five inputs connected to said register means and receiving respectively the number of an intermediate time switch, the number of an intermediate line, data discriminating between an incoming and outgoing line, the indication of the group to which the output time switch of an outgoing line belongs, and the indication of the group to which the input time switch of an incoming line belongs.
Claim 5
Dependent Claim
65 words
Device according to claim 3, characterized in that said register means includes a register receiving the indication of the number of the output time switch in question comprising six binary elements, one binary element of which corresponding to the first or second network to which the output time switch belongs, this information being transmitted to the gates associated with the words of the block memory.
Claim 6
Dependent Claim
65 words
Device according to claim 3, characterized in that said register means includes a register receiving the indication of the designation of the input time switch in question comprising six binary elements, one binary element of which corresponding to the first or second network to which the input time switch belongs, this indication being transmitted to the gates associated with the words of the block memory.
Claim 7
Dependent Claim
65 words
Device according to claim 5, characterized in that said register means includes a register receiving the indication of the number of the output time switch in question comprising six binary elements, one binary element of which corresponding to the first or second network to which the output time switch belongs, this information being transmitted to the gates associated with the words of the block memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-09 | 1976-10-09 | 1977-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-09 | 1980-10-09 | 1981-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-09 | 1984-10-09 | 1985-04-10 | $7700.00 | Window Closed / Lapsed |