Cross-point-switching arrangement

Claim 2

A crosspoint-switching arrangement comprising: a. array terminal circuitry including line/trunk circuits and link circuits; b. a switching array of semiconductor cross-points said line/truck circuits and link circuits, said path said line/trunk circuits and link circuits, said switching array including a primary stage, a secondary stage, and at least one intermediate stage; c. path selection control means coupled between said path selection control means including an array scanner; d. array control gating means including primary stage-gating circuitry coupled to said switching array and to said path selection control means, and intermediate stage-gating circuitry coupled to said switching array and to said primary stage-gating circuitry, wherein said primary gating circuitry includes a separate AND-gate circuit operatively connected to each vertical row of said cross-points within said primary stAge; and e. an input source to said array terminal circuitry means causing in response thereto said path selection control means to establish in said switching array by way of said array control-gating means a complete path by selecting and energizing the minimum number of array cross-points required to complete a connection between said line/trunk circuits and link circuits.

Claim 3

A crosspoint-switching arrangement comprising: a. array terminal circuitry including line/trunk circuits and link circuits; b. a switching array of semiconductor cross-points coupled between said line/trunk circuits and link circuits, said switching array including a primary stage, a secondary stage, and at least one intermediate stage; c. path selection control means coupled between said line/trunk circuits and link circuits, said path selection control means including an array scanner; d. array control-gating means including primary stage-gating circuitry coupled to said switching array and to said path selection control means, and intermediate stage circuitry coupled to said switching array and to said primary stage-gating circuitry, said intermediate stage-gating circuitry including a separate and identical blocking detector network associated with each coordinate matrix group subdivision of said intermediate stage; and e. an input source to said array terminal circuitry means causing in response thereto said path selection control means to establish in said switching array by way of said array control-gating means a complete path by selecting and energizing the minimum number of array cross-points required to complete a connection between said line/trunk circuits and link circuits.

Claim 4

A crosspoint-switching arrangement comprising: a. array terminal circuitry including line/trunk circuits and link circuits; b. a switching array of semiconductor cross-points coupled between said line/trunk circuits and link circuits, said switching array including a primary stage, a secondary stage, and at least one intermediate stage; c. path selection control means coupled between said line/trunk circuits and link circuits, said path selection control means including an array scanner; d. array control-gating means including primary stage-gating circuitry coupled to said switching array and to said path selection control means, and intermediate stage circuitry coupled to said switching array and to said primary stage-gating circuitry, said intermediate stage-gating circuitry including a separate and identical blocking detector network associated with each coordinate matrix group subdivision of said intermediate stage; and e. an input source to said array terminal circuitry means causing in response thereto said path selection control means to establish in said switching array by way of said array control-gating means a complete path by selecting and energizing the minimum number of array cross-points required to complete a connection between said line/trunk circuits and link circuits.

Claim 5

A crosspoint-switching arrangement comprising: a. array terminal circuitry including line/trunk circuits and link circuits; b. a switching array of semiconductor cross-points coupled between said line/trunk circuits and link circuits, said switching array including a primary stage, a secondary stage, and at least one intermediate stage; c. path selection control means coupled between said line/trunk circuits and link circuits, said path selection control means including an array scanner; d. array control-gating means coupled to said path selection control means and said switching array; e. an input source to said array terminal circuitry means causing in response thereto said path selection control means to establish in said switching array by way of said array control-gating means a complete path by selecting and energizing the minimum number of array cross-points required to complete a connection between said line/trunk circuits and link circuits; and f. fault-determining means including fault indication circuitry coupled to said switching array and to said path selection control means, and fault detector means coupled to said array terminal circuitry, to said array control-gating means and to said fault indication circuitry, for determining cross-point failure in response to an initiating signal from said path selection control means.

Claim 6

A crosspoint-switching arrangement comprising: a. array terminal circuitry including line/trunk circuits and link circuits; b. a switching array of semiconductor cross-points coupled between said line/trunk circuits and link circuits, said switching array including a primary stage, a secondary stage, and at least one intermediate stage; c. path selection control means coupled between said line/trunk circuits and link circuits, said path selection control means including an array scanner; d. array control-gating means coupled to said path selection control means and said switching array; e. an input source to said array terminal circuitry means causing in response thereto said path selection control means to establish in said switching array by way of said array control-gating means a complete path by selecting and energizing the minimum number of array cross-points required to complete a connection between said line/trunk circuits and link circuits; and f. fault-determining means including fault indication circuitry coupled to said switching array and to said path selection control means, and fault detector means coupled to said array terminal circuitry, to said array control-gating means and to said fault indication circuitry, for determining cross-point failure in response to an initiating signal from said path selection control means.

Claim 7

A crosspoint-switching arrangement according to claim 3 wherein said array control-gating means include primary stage-gating circuitry coupled to said switching array and to said path selection control means, and intermediate stage-gating circuitry coupled to said switching array and to said primary stage-gating circuitry.

Claim 8

A crosspoint-switching arrangement according to claim 3 wherein said switching array may include separate transmit and receive arrays, each having a primary stage, a secondary stage, and at least one intermediate stage.

Claim 9

A crosspoint-switching arrangement according to claim 3 wherein each stage is subdivided into a plurality of coordinate matrix groups with the cross-points thereof being interconnected in vertical and horizontal rows and wherein each cross-point has the same functional electrode associated with a vertical row and a second functional electrode associated with a horiZontal row.

Claim 10

A crosspoint-switching arrangement according to claim 6 wherein each vertical row of an array stage is connected to a horizontal row belonging to the adjacent and succeeding stage such that each coordinate matrix group of said array stage has at least one interconnection with each coordinate matrix group of said adjacent and succeeding stage.

Claim 11

A crosspoint-switching arrangement according to claim 7 wherein the horizontal rows of said primary array stage represent the inputs to said switching array and wherein the vertical rows of said secondary array stage represent the outputs of said switching array.

Claim 12

A crosspoint-switching arrangement according to claim 4 wherein said primary stage-gating circuitry includes separate and identical gating circuitry associated with each coordinate matrix group within said primary stage.

Claim 13

A crosspoint-switching arrangement according to claim 9 wherein said separate and identical gating circuitry includes AND-gating circuitry in which a separate and identical AND-gated circuit is operatively connected to each vertical row of said coordinate matrix group.

Claim 14

A crosspoint-switching arrangement according to claim 10 wherein the AND-gated circuits associated with like-numbered vertical rows have at least one common input.

Claim 15

A crosspoint-switching arrangement according to claim 11 wherein said AND-gated circuits associated with like-numbered primary stage vertical rows have a common time slot input such that each set of like-numbered vertical rows has a different time slot input.

Claim 16

A crosspoint-switching arrangement according to claim 10 wherein the AND-gated circuits associated with a coordinate matrix group have a common input.

Claim 17

A crosspoint-switching arrangement according to claim 9 wherein said separate and identical gating circuitry further includes busy check OR-gating circuitry wherein each busy check OR-gate circuit is connected to all vertical rows of the respective primary stage coordinate matrix group.

Claim 18

A crosspoint-switching arrangement according to claim 14 wherein said busy check OR-gate circuits have a common output connection.

Claim 19

A crosspoint-switching arrangement according to claim 4 wherein said intermediate stage-gating circuitry includes separate and identical blocking detector networks associated with each intermediate stage coordinate matrix group.

Claim 20

A crosspoint-switching arrangement according to claim 16 wherein each said block detector network is coupled to the vertical rows of its respective intermediate stage coordinate matrix group, and is coupled to said common input of said AND-gated circuits associated with like-numbered primary stage vertical rows.

Claim 21

A crosspoint-switching arrangement according to claim 17 wherein each blocking detector network output is coupled to a different common input such that each network is coupled to a different set of said primary stage AND-gated circuits associated with like-numbered vertical rows, and that there exists an intermediate coordinate matrix group and corresponding blocking detector network for each of the sets of like-numbered primary stage vertical rows.

Claim 22

A crosspoint-switching arrangement according to claim 3 wherein said fault-determining means include differentiator circuitry coupled to said array, and check-gating circuitry coupled to said differentiator circuitry.

Claim 23

A crosspoint-switching arrangement according to claim 19 wherein said differentiator circuitry includes separate differentiating circuitry for each array stage and wherein said separate differentiating circuitry generates a pulse corresponding to an input to said gating circuitry in response to the activation of an array stage cross-point

Claim 24

A crosspoint-switching arrangement according to claim 20 wherein said separate differentiating circuitry for each array stage includes individual and identical differentiator circuits associated with each coordinate matrix group within the intermediate and secondary stageS, said individual and identical differentiator circuits of a respective stage having a common output corresponding to said input to the gating circuitry.

Claim 25

A crosspoint-switching arrangement according to claim 21 wherein each said individual and identical differentiator circuit of the intermediate stage is coupled to the blocking detector network of its respective coordinate matrix group whereby the voltage change resulting from any cross-point firing within that group is sensed at the output of said blocking detector network and transferred to the gating circuitry by said differentiator circuit.

Claim 26

A crosspoint-switching arrangement according to claim 22 wherein each said individual and identical differentiator circuit of said secondary stage is operatively coupled to the vertical rows of its respective coordinate matrix group whereby each said differentiator circuit responds to a voltage change resulting from activation of a cross-point within that group by generating an output to said gating circuitry.

Claim 27

A crosspoint-switching arrangement according to claim 20 wherein said separate differentiating circuitry for each array stage further includes a primary stage differentiator circuit operatively connected to the common interconnection of said busy check OR-gate circuitry, and wherein said primary stage differentiator circuit generates an output to said gating circuitry in response to the activation of a primary stage cross-point.

Claim 28

A crosspoint-switching arrangement according to claim 19 wherein said fault-determining gating circuitry includes at least one separate check AND-gate circuit for each array stage, and wherein said check AND-gate circuits have a common input in the form of said input signal from the path selection control means.

Claim 29

A crosspoint-switching arrangement according to claim 25 wherein said at least one check AND-gate circuit associated with the primary stage is coupled to the corresponding primary stage differentiator circuit such that said check AND-gate circuit presents an output upon interrogation by said input signal from the path selection control means whenever a primary stage cross-point has fired.

Claim 30

A crosspoint-switching arrangement according to claim 25 wherein said check AND-gate circuit associated with the intermediate stage is coupled to said common output of the intermediate stage individual and identical differentiator circuits, and wherein said AND-gate circuit associated with the secondary stage is coupled to said common output of the secondary stage individual and identical differentiator circuits, such that the respective check AND-gate circuits present an output upon interrogation by said path selection control means whenever a cross-point of the respective array stage has fired.