Output buffer circuit of semiconductor integrated circuit

Claim 2

An output buffer for producing an output data at an output terminal in response to an input signal comprising: a first MOS transistor for charging said output terminal toward a first supply potential when said input signal changes to a first logic level, including a source and drain connected between said output terminal and a first supply potential terminal, and a gate; a first control means, coupled to the input signal and to the gate of the first MOS transistor, for controlling a potential of the gate of the first MOS transistor; a second MOS transistor for discharging said output terminal toward a second supply potential when said input signal changes to a second logic level, including a source and drain connected between said output terminal and a second supply potential terminal, and a gate substantially isolated from the second supply potential during the time the input signal is at the second logic level; and a second control means, coupled to the input signal and to the gate of the second MOS transistor, for controlling a potential of the gate of the second MOS transistor by charging said gate of the second MOS transistor toward a first supply potential, including resistance means having one end connected to the gate of said second MOS transistor and having a substantially constant resistance value, and a third MOS transistor having a drain coupled to the other end of the resistance means, a source coupled to the first supply potential terminal, and a gate coupled to the input signal; wherein during the time when the input signal is at the second logic level the gate of the second transistor is sufficiently isolated from the second supply potential whereby a decreasing current flowing through the resistance means charges the gate at a gradually decreasing rate.

Claim 3

The output buffer according to claim 1, wherein said first MOS transistor is a p-channel type and said second MOS transistor is an N-channel type.

Claim 4

The output buffer according to claim 1, wherein said resistance means includes a resistive element composed of polysilicon.

Claim 5

The output buffer according to claim 1, wherein said resistance means includes resistive element composed of an N + diffusion layer.

Claim 6

The output buffer according to claim 1, wherein said resistance means includes a resistive element composed of a p + diffusion layer.

Claim 7

The output buffer according to claim 1, wherein said resistance means includes a fourth MOS transistor.

Claim 8

The output buffer according to claim 6, wherein said fourth MOS transistor is a depletion-type N-channel transistor.

Claim 9

The output buffer according to claim 1, wherein said resistance means includes plurality of MOS transistors coupled in parallel with each other.

Claim 10

The output buffer according to claim 1, wherein a resistance value of said resistance means and that of said third MOS transistor are nearly equal when they charge said gate of said second MOS transistor.

Claim 11

In a circuit having first and second supply potential terminals and first and second logic levels, an output buffer for producing an output data at an output terminal in response to an input signal, comprising: a first MOS transistor for charging the output terminal toward a first supply potential when the input signal changes to a first logic level, including a source and drain coupled between the output terminal and the first supply potential terminal, and a gate; a first control means, coupled to the input signal and to the gate of the first MOS transistor, for controlling a potential of the gate of the first MOS transistor, including a second MOS transistor having a source and drain coupled between the gate of the first MOS transistor and the first supply potential terminal and a third transistor having a source and drain coupled between the gate of the first MOS transistor and the second supply potential terminal; a fourth MOS transistor for discharging the output terminal toward a second supply potential when the input signal changes to a second logic level, including a source and drain coupled between the output terminal and a second supply potential terminal, and a gate substantially isolated from the second supply potential during the time the input signal is at the second logic level; and a second control means, coupled to the input signal and to the gate of the fourth MOS transistor, for controlling a potential of the gate of the fourth MOS transistor, by charging the gate of the fourth MOS transistor toward a first supply potential, including resistance means having one end connected to the gate of the fourth MOS transistor and having a substantially constant resistance value, a fifth MOS transistor having a drain coupled to the other end of the resistance means, a source coupled to the first supply potential terminal, and a gate coupled to the input signal; a sixth MOS transistor for decreasing a gate potential of the fourth transistor when the input signal changes to the first logic level having a source and drain coupled between the gate of the fourth MOS transistor and the second supply potential terminal, wherein during the time when the input signal is at the second logic level the gate of the second transistor is sufficiently isolated from the second supply potential whereby a decreasing current flowing through the resistance means charges the gate with a gradually decreasing of a charging speed.

Claim 12

In a circuit having first and second supply potential terminals and first and second logic levels, an output buffer for producing an output data at an output terminal in response to an input signal, comprising: a first MOS transistor for charging the output terminal toward a first supply potential when the input signal changes to a first logic level, including a source and drain coupled between the output terminal and the first supply potential terminal, and a gate; a first control means, coupled to the input signal and to the gate of the first MOS transistor, for controlling a potential of the gate of the first MOS transistor, including a second MOS transistor having a source and drain coupled between the gate of the first MOS transistor and the first supply potential terminal and a third transistor having a source and drain coupled between the gate of the first MOS transistor and the second supply potential terminal; a fourth MOS transistor for discharging the output terminal toward a second supply potential when the input signal changes to a second logic level, including a source and drain coupled between the output terminal and a second supply potential terminal, and a gate substantially isolated from the second supply potential during the time the input signal is at the second logic level; and a second control means, coupled to the input signal and to the gate of the fourth MOS transistor, for controlling a potential of the gate of the fourth MOS transistor, by charging the gate of the fourth MOS transistor toward a first supply potential, including resistance means having one end connected to the gate of the fourth MOS transistor and having a substantially constant resistance value, a fifth MOS transistor having a drain coupled to the other end of the resistance means, a source coupled to the first supply potential terminal, and a gate coupled to the input signal; a sixth MOS transistor for decreasing a gate potential of the fourth transistor when the input signal changes to the first logic level having a source and drain coupled between the gate of the fourth MOS transistor and the second supply potential terminal, wherein during the time when the input signal is at the second logic level the gate of the second transistor is sufficiently isolated from the second supply potential whereby a decreasing current flowing through the resistance means charges the gate with a gradually decreasing of a charging speed.

Claim 13

The output buffer according to claim 10, wherein the first MOS transistor is a P-channel type and the fourth MOS transistor is an N-channel type.

Claim 14

The output buffer according to claim 10, wherein the resistance means includes a resistive element composed of polysilicon.

Claim 15

The output buffer according to claim 10, wherein the resistance means includes a resistive element composed of an N+ diffusion layer.

Claim 16

The output buffer according to claim 10, wherein the resistance means includes a plurality of MOS transistors coupled in parallel with each other.

Claim 17

The output buffer according to claim 10, wherein a resistance value of the resistance means and that of the fifth MOS transistor are nearly equal when they charge the gate of the fourth MOS transistor.

Claim 18

The output buffer according to claim 10, wherein said resistance means include a resistive element composed of a P + diffusion layer.

Claim 19

The output buffer according to claim 10, wherein said resistance means includes a seventh MOS transistor.

Claim 20

The output buffer according to claim 17, wherein said seventh MOS transistor is a depletion-type N-channel transistor.

Claim 21

The output buffer according to claim 17, wherein said fifth MOS transistor is a P-channel type and said seventh MOS transistor is an N-channel type.

Claim 22

In a circuit having first and second supply potential terminals and first and second logic levels, an output buffer for producing an output data at an output terminal in response to an input signal, comprising: a first MOS transistor for charging the output terminal toward a first supply potential when the input signal changes to a first logic level, including a source and drain coupled between the output terminal and the first supply potential terminal, and a gate; a first control means, coupled to the input signal and to the gate of the first MOS transistor, for controlling a potential of the gate of the first MOS transistor, by charging the gate of the first MOS transistor toward a first supply potential, including a first resistance means having one end connected to the gate of the first MOS transistor and having a substantially constant resistance value, a second MOS transistor having a drain coupled to the other end of the resistance means, a source coupled to the second supply potential terminal, and a gate coupled to the input signal; a third MOS transistor for increasing a gate potential of the first transistor when the input signal changes to the second logic level having a source and drain coupled between the gate of the fourth MOS transistor and the second supply potential terminal, a fourth MOS transistor for discharging the output terminal toward a second supply potential when the input signal changes to a second logic level, including a source and drain coupled between the output terminal and a second supply potential terminal, and a gate substantially isolated from the second supply potential during the time the input signal is at the second logic level; and a second control means, coupled to the input signal and to the gate of the fourth MOS transistor, for controlling a potential of the gate of the fourth MOS transistor, by charging the gate of the fourth MOS transistor toward a first supply potential, including second resistance means having one end connected to the gate of the fourth MOS transistor and having a substantially constant resistance value, a fifth MOS transistor having a drain coupled to the other end of the resistance means, a source coupled to the first supply potential terminal, and a gate coupled to the input signal; a sixth MOS transistor for decreasing a gate potential of the fourth transistor when the input signal changes to the first logic level having a source and drain coupled between the gate of the fourth MOS transistor and the second supply potential terminal, wherein during the time when the input signal is at the second logic level the gate of the second transistor is sufficiently isolated from the second supply potential whereby a decreasing current flowing through the resistance means charges the gate with a gradually decreasing of a charging speed.

Claim 23

In a circuit having first and second supply potential terminals and first and second logic levels, an output buffer for producing an output data at an output terminal in response to an input signal, comprising: a first MOS transistor for charging the output terminal toward a first supply potential when the input signal changes to a first logic level, including a source and drain coupled between the output terminal and the first supply potential terminal, and a gate; a first control means, coupled to the input signal and to the gate of the first MOS transistor, for controlling a potential of the gate of the first MOS transistor, by charging the gate of the first MOS transistor toward a first supply potential, including a first resistance means having one end connected to the gate of the first MOS transistor and having a substantially constant resistance value, a second MOS transistor having a drain coupled to the other end of the resistance means, a source coupled to the second supply potential terminal, and a gate coupled to the input signal; a third MOS transistor for increasing a gate potential of the first transistor when the input signal changes to the second logic level having a source and drain coupled between the gate of the fourth MOS transistor and the second supply potential terminal, a fourth MOS transistor for discharging the output terminal toward a second supply potential when the input signal changes to a second logic level, including a source and drain coupled between the output terminal and a second supply potential terminal, and a gate substantially isolated from the second supply potential during the time the input signal is at the second logic level; and a second control means, coupled to the input signal and to the gate of the fourth MOS transistor, for controlling a potential of the gate of the fourth MOS transistor, by charging the gate of the fourth MOS transistor toward a first supply potential, including second resistance means having one end connected to the gate of the fourth MOS transistor and having a substantially constant resistance value, a fifth MOS transistor having a drain coupled to the other end of the resistance means, a source coupled to the first supply potential terminal, and a gate coupled to the input signal; a sixth MOS transistor for decreasing a gate potential of the fourth transistor when the input signal changes to the first logic level having a source and drain coupled between the gate of the fourth MOS transistor and the second supply potential terminal, wherein during the time when the input signal is at the second logic level the gate of the second transistor is sufficiently isolated from the second supply potential whereby a decreasing current flowing through the resistance means charges the gate with a gradually decreasing of a charging speed.

Claim 24

The output buffer according to claim 20, wherein the third MOS transistor is a N-channel type and said fourth MOS transistor is an P-channel type.