Patent US5380678A successfully refreshed from Google Patents.
Patent US4984050A successfully refreshed from Google Patents.
US4984050A
Expired / Lapsed
US
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Gate-array type intergated circuit semiconductor device
Assignee: NEC Corp
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Filing: 1989-01-13
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Granted: 1991-01-08
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Expires: 2009-01-13
Abstract
Abstract A gate array type integrated circuit semiconductor device includes a semiconductor substrate, in a basic cell forming portion of which are formed a plurality of impurity regions of basic circuit elements. The impurity regions form a plurality of basic cells. A field insulating layer is also formed on the substrate, which is partially embedded in the major surface of the substrate and is formed entirely on a wiring channel forming portion of the substrate and selectively on the basic cell forming portion of the same to surround each of the impurity regions. An insulating film is formed on the field insulating layer. A wiring structure is provided, which includes mutual wirings formed of a first level conductive layer, internal wirings, and interconnecting wirings formed of a second level conductive layer higher than the first level conductive layer. Each of the mutual wirings is formed only on the insulating film formed on the wiring channel forming portion and is connected to the impurity regions through the interconnecting and internal wirings.
Inventors
- 👤 Masaharu Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/901; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/906
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
316 words
A gate-array type integrated circuit semiconductor device comprising: a semiconductor substrate having a major surface and provided with a basic cell forming portion and a wiring channel forming portion, said wiring channel forming portion extending in a first direction; a plurality of impurity regions of basic circuit elements formed in said basic cell forming portion to form a plurality of basic cells which constitute a plurality of basic cell lines on said substrate; a field insulating layer formed on said substrate, said field insulating layer being partially embedded in said major surface of said substrate and being formed entirely on said wiring channel forming portion and selectively on said basic cell forming portion so as to surround each of said impurity regions of said basic circuit element; a first insulating film having a first thickness and formed on said field insulating layer formed on said wiring channel forming portion without extending onto said basic cell forming portion, said first insulating film extending in said first direction with a constant width; and a wiring structure including mutual wirings formed of a first level conductive layer, internal wirings formed of said first level conductive layer, and interconnecting wirings formed of a second level conductive layer higher than that of said first level conductive layer, each of said mutual wirings being formed only on said first insulating film formed on said wiring channel forming portion and extending in said first direction and being connected to said impurity regions through said interconnecting and internal wirings, each of said internal wirings being formed only on said basic cell forming portion and being connected to one of said impurity regions without interposing any other wiring, and each of said interconnecting wirings connecting an internal wiring on said basic cell forming portion with a mutual wiring on said wiring channel forming portion and extending in a second direction perpendicular to said first direction.
Claim 2
Dependent Claim
316 words
A gate-array type integrated circuit semiconductor device comprising: a semiconductor substrate having a major surface and provided with a basic cell forming portion and a wiring channel forming portion, said wiring channel forming portion extending in a first direction; a plurality of impurity regions of basic circuit elements formed in said basic cell forming portion to form a plurality of basic cells which constitute a plurality of basic cell lines on said substrate; a field insulating layer formed on said substrate, said field insulating layer being partially embedded in said major surface of said substrate and being formed entirely on said wiring channel forming portion and selectively on said basic cell forming portion so as to surround each of said impurity regions of said basic circuit element; a first insulating film having a first thickness and formed on said field insulating layer formed on said wiring channel forming portion without extending onto said basic cell forming portion, said first insulating film extending in said first direction with a constant width; and a wiring structure including mutual wirings formed of a first level conductive layer, internal wirings formed of said first level conductive layer, and interconnecting wirings formed of a second level conductive layer higher than that of said first level conductive layer, each of said mutual wirings being formed only on said first insulating film formed on said wiring channel forming portion and extending in said first direction and being connected to said impurity regions through said interconnecting and internal wirings, each of said internal wirings being formed only on said basic cell forming portion and being connected to one of said impurity regions without interposing any other wiring, and each of said interconnecting wirings connecting an internal wiring on said basic cell forming portion with a mutual wiring on said wiring channel forming portion and extending in a second direction perpendicular to said first direction.
Claim 3
Dependent Claim
86 words
The gate-array type integrated circuit semiconductor device of claim 1, and further comprising a second insulating film having a second thickness less than said first thickness of said first insulating film and covering said first insulating film, said field insulating layer and said impurity regions of said basic circuit elements such that said mutual wirings are attached to said second insulating film above said wiring channel forming portion and that said internal wirings are attached to said second insulating film on said basic cell forming portion.
Claim 4
Dependent Claim
22 words
The gate-array type integrated circuit semiconductor device of claim 1, wherein said first and second level conductive layers are made of aluminum.
Claim 5
Dependent Claim
22 words
The gate-array type integrated circuit semiconductor device of claim 2, wherein said first and second insulating films are made of silicon oxide.
Claim 6
Dependent Claim
23 words
The gate-array type integrated circuit semiconductor device of claim 1, and further comprising peripheral circuits formed on a peripheral portion of said substrate.
Claim 7
Dependent Claim
21 words
The gate-array type integrated circuit semiconductor device of claim 5, wherein said peripheral circuits are input/output buffer circuits of the device.
Claim 8
Dependent Claim
28 words
The gate-array type integrated circuit semiconductor device of claim 1, wherein said first insulating film has a thickness of 0.7 μm or more and 1.5 μm or less.
Claim 9
Dependent Claim
46 words
The gate-array type integrated circuit semiconductor device of clam 2, wherein said first insulating film has a thickness of 0.7 μm or more and 1.5 μm or less, and said second insulating film has a thickness of 0.2 μm or more and 0.5 μm or less.
Claim 10
Dependent Claim
46 words
The gate-array type integrated circuit semiconductor device of clam 2, wherein said first insulating film has a thickness of 0.7 μm or more and 1.5 μm or less, and said second insulating film has a thickness of 0.2 μm or more and 0.5 μm or less.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-07 | 1994-07-09 | 1995-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-07 | 1998-07-09 | 1999-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-07 | 2002-07-09 | 2003-01-08 | $7700.00 | Window Closed / Lapsed |