US4417265A
Expired / Lapsed
US
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Lateral PNP power transistor
Assignee: National Semiconductor Corp
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Filing: 1981-03-26
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Granted: 1983-11-22
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Expires: 2001-03-26
Abstract
Abstract A high current lateral transistor suitable for intergrated circuit construction is fabricated in the form of a plurality of parallel transistors. Each transistor has an emitter surrounded by a closely confronting collector with the intervening semiconductor acting as the base region. Groups of parallel connected transistors are located on both sides of and distributed along a centerline which contains a number of diffused crossunder resistor elements. Each group of transistors is flanked on both sides by a base contact that is extended perpendicularly away from the centerline and connected by metalization to a resistor element. The resistor elements act to distribute the transistor base currents in a ballasting operation that promotes proper current distribution. Since the resistors are under the oxide the emitter and collector metalization can pass across the centerline region and parallel connect the individual transistors.
Inventors
- 👤 Judd R. Murkland
- 👤 James S. Congdon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:06
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/121; H10D84/125; H10D10/00; H10D10/60; H10D84/60; H10D84/645
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
181 words
A lateral power transistor suitable for construction into a semiconductor substrate having a planar surface oxide, said transistor comprising: a plurality of parallel connecting individual transistor elements arrayed in groups of elements located within the surface of a semiconductor having one conductivity type, each element having an emitter of the opposite semiconductor conductivity type confronted by a spaced apart collector of said opposite conductivity type, wherein the space between said emitter and collector constitutes a base region; said groups being located on opposite sides of and disposed along a center region; means adjacent to each of said groups for making distributed contact to said transistor base regions therein, crossunder resistance means located within said center region for making resistance connections to said distributed contact means whereby the base currents in said transistor elements are ballasted and equalized; and metalization located on top of said semiconductor oxide for interconnecting said transistor elements into a unitary device in which said metalization can be run directly over said center region thereby permitting said groups to be parallel connected without interfering with said base connections.
Claim 2
Dependent Claim
181 words
A lateral power transistor suitable for construction into a semiconductor substrate having a planar surface oxide, said transistor comprising: a plurality of parallel connecting individual transistor elements arrayed in groups of elements located within the surface of a semiconductor having one conductivity type, each element having an emitter of the opposite semiconductor conductivity type confronted by a spaced apart collector of said opposite conductivity type, wherein the space between said emitter and collector constitutes a base region; said groups being located on opposite sides of and disposed along a center region; means adjacent to each of said groups for making distributed contact to said transistor base regions therein, crossunder resistance means located within said center region for making resistance connections to said distributed contact means whereby the base currents in said transistor elements are ballasted and equalized; and metalization located on top of said semiconductor oxide for interconnecting said transistor elements into a unitary device in which said metalization can be run directly over said center region thereby permitting said groups to be parallel connected without interfering with said base connections.
Claim 3
Dependent Claim
20 words
The transistor of claim 1 wherein said groups are contained within a single PN junction isolated region of semiconductor material.
Claim 4
Dependent Claim
25 words
The transistor of claim 2 wherein a conductive buried layer underlies said isolated region and said distributed contact means makes a low resistance connection thereto.
Claim 5
Dependent Claim
56 words
The transistor of claim 2 wherein said crossunder resistance means comprises a first diffused region of semiconductor of a conductivity type opposite to that of said isolated region and a second diffused region having a conductivity type the same as said isolated region confined within said first diffused region and contoured to create said resistance connections.
Claim 6
Dependent Claim
27 words
The transistor of claim 4 wherein said first and second diffused regions are connected together at one end which comprises the base terminal connection for said transistor.
Claim 7
Dependent Claim
168 words
A composite lateral transistor suitable for incorporation into a bipolar monolithic semiconductor integrated circuit, said composite transistor including a plurality of individual lateral transistor elements connected together to provide a common base feed connection, a common collector terminal and a common emitter terminal, said composite transistor comprising: a semiconductor substrate having a planar oxide thereon; a plurality of individual lateral transistors fabricated into the surface of said semiconductor, said plurality being arrayed in at least two groups located on opposite sides of a centerline region, each group including a plurality of rows of individual lateral transistors, a resistive element fabricated in the surface of said semiconductor substrate in said centerline region and including separate resistor elements for each of said groups, one end of said resistive region acting to provide said common base feed connection and metalization on top of said planar oxide extending across said centerline region to parallel interconnect the emitters and collectors of said individual lateral transistors to provide said common emitter and collector terminals.
Claim 8
Dependent Claim
168 words
A composite lateral transistor suitable for incorporation into a bipolar monolithic semiconductor integrated circuit, said composite transistor including a plurality of individual lateral transistor elements connected together to provide a common base feed connection, a common collector terminal and a common emitter terminal, said composite transistor comprising: a semiconductor substrate having a planar oxide thereon; a plurality of individual lateral transistors fabricated into the surface of said semiconductor, said plurality being arrayed in at least two groups located on opposite sides of a centerline region, each group including a plurality of rows of individual lateral transistors, a resistive element fabricated in the surface of said semiconductor substrate in said centerline region and including separate resistor elements for each of said groups, one end of said resistive region acting to provide said common base feed connection and metalization on top of said planar oxide extending across said centerline region to parallel interconnect the emitters and collectors of said individual lateral transistors to provide said common emitter and collector terminals.
Claim 9
Dependent Claim
20 words
The transistor of claim 6 wherein said resistive element comprises a diffused region contoured to provide the desired resistance value.
Claim 10
Dependent Claim
47 words
The transistor of claim 7 wherein said resistive region comprises a first diffused region having a conductivity type opposite that of said semiconductor substrate and a second diffused region inside said first diffused region and said second diffused region having the same conductivity type as said semiconductor.
Claim 11
Dependent Claim
22 words
The transistor of claim 8 wherein said first and second diffused regions are connected together to provide said common base feed connection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-21 | 1987-05-23 | 1987-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-21 | 1991-05-23 | 1991-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-21 | 1995-05-23 | 1995-11-22 | $7700.00 | Window Closed / Lapsed |