US4983251A
Expired / Lapsed
US
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Method of manufacturing semiconductor devices
Assignee: NXP BV
•
Filing: 1986-06-16
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Granted: 1991-01-08
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Expires: 2006-06-16
Abstract
Abstract A method for manufacturing a semiconductor device comprising at least a support body and a monocrystalline semiconductor body, in which both bodies are provided with at least one flat optically smooth surface obtained by means of bulk-reducing polishing (mirror polishing), and at least the semiconductor body is then provided at the optically smooth surface with an electrically insulating layer with at least the electrically insulating layer on the semiconductor body being subjected to a bonding-activating operation, whereupon both bodies after their flat surfaces have been cleaned, are contacted with each other in a dust-free atmosphere in order to obtain a rigid mechanical connection, after which they are subjected to a heat treatment of at least 250° C., whereupon the semiconductor body is etched to a thin layer having a thickness lying between 0.05 and 100 μm.
Inventors
- 👤 Jan Haisma
- 👤 Theodorus M. Michielsen
- 👤 Jan A. Pals
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D62/00; H10D62/10; H10D62/117; H10D88/00; H10D88/01; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181; H10W70/00; H10W70/099; H10W72/00; H10W72/30; H10W90/00; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/834; H10W90/20; H10W90/22; Y; Y10; Y10S; Y10S148/00; Y10S148/012
Claims Analysis
Total Claims: 47
Claim 1
Independent Claim
189 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (b) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (c) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, wherein said bonding-activating operation is a light surface smoothing operation or a chemical etching operation, (d) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (e) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350° C., (f) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (g) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns.
Claim 2
Independent Claim
189 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (b) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (c) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, wherein said bonding-activating operation is a light surface smoothing operation or a chemical etching operation, (d) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (e) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350° C., (f) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (g) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns.
Claim 3
Dependent Claim
21 words
A method according to claim 1, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.
Claim 4
Dependent Claim
21 words
A method according to claim 1, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.
Claim 5
Dependent Claim
37 words
A method according to claim 1 or claim 2 or claim 3, wherein said step of thinning by etching is carried out by an isotropic etching technique, and wherein said monocrystalline semiconductor body is intrinsic or doped.
Claim 6
Dependent Claim
99 words
A method according to claim 1 or claim 2 or claim 3 further comprising: etching said thinned monocrystalline semiconductor body to form a plurality of separate regions, closing, by thermal oxidation or by deposition, spaces between said separate regions wherein deposition comprises depositing an insulating groove filling in said spaces between said separate regions, depositing insulating filling on said separate regions to a thickness exceeding the thickness of said thinned monocrystalline semiconductor body, planarizing the monocrystalline semiconductor body with the insulating filling thereon to thereby form a support of insulated semiconductor regions the surface of which is entirely flat.
Claim 7
Dependent Claim
109 words
A method according to claim 1 or claim 2 or claim 3 wherein a portion of said support body is formed with semiconductor material of AIII-BV type, said portion being contiguous with said optically smooth surface, wherein said monocrystalline semiconductor body is formed of silicon and said electrically insulating layer is formed of thermally grown silicon oxide, and further comprising: removing portions of said monocrystalline semiconductor body to said silicon oxide, forming doped regions constituting source and drain regions in said AIII-BV semiconductor material, and forming gate regions from said electrically insulating layer of silicon oxide between said doped regions for a MOS FET of said AIII-BV semiconductor material.
Claim 8
Dependent Claim
14 words
A method according to claim 6, wherein said AIII-BV semiconductor material is gallium arsenide.
Claim 9
Dependent Claim
27 words
A method according to claim 1 or claim 2 or claim 3, wherein said support body is formed with both electrical insulating properties and active bulk properties.
Claim 10
Dependent Claim
25 words
A method according to claim 8, wherein said active bulk properties include at least one of magnetic properties, piezoelectrical properties, photoreactive properties, and electrooptical properties.
Claim 11
Dependent Claim
32 words
A method according to claim 1 or claim 2 or claim 3, wherein said support body is formed with electrically insulating properties, layerwise active properties, and properties for producing static-magnetic surface waves.
Claim 12
Dependent Claim
16 words
A method according to claim 10, wherein said layerwise active properties include generating acoustic surface waves.
Claim 13
Dependent Claim
120 words
A method according to claim 1 or 2 or 3 further comprising: forming IC structures in the thinned monocrystalline semiconductor body to thereby form a first embossed outer surface, said IC structures forming a first register, depositing a silicon oxide layer on said first embossed outer surface, planarizing said silicon oxide layer to form an insulating layer of small thickness, forming a second thinned monocrystalline semiconductor body having an electrically insulating layer on said planarized silicon oxide layer, forming IC structures in said second thinned monocrystalline semiconductor body to thereby form a second embossed outer surface, said IC structures forming a second register, carrying out a repetition of analogous steps to form additional ICs thereby forming a three-dimensional stack IC.
Claim 14
Dependent Claim
27 words
A method according to claim 12, wherein at least one Peltier element is formed in at least one of said registers for cooling said three-dimensional stack IC.
Claim 15
Dependent Claim
23 words
A method according to claim 12, wherein at least one of said registers is used to accommodate components occupying a large surface area.
Claim 16
Dependent Claim
11 words
A method according to claim 14, wherein said components are capacitors.
Claim 17
Dependent Claim
27 words
A method according to claim 12 further comprising: etching holes into said registers at location accommodating electrical connections, and filling said holes with an electrically conducting material.
Claim 18
Dependent Claim
26 words
A method according to claim 12, further comprising providing electrical conductors at the outer circumference of said three-dimensional stack IC to establish connections between different registers.
Claim 19
Dependent Claim
42 words
A method according to claim 12 further comprising: providing an optical fiber arrangement to feed light energy to at least one of said registers, and providing transparent channels in said three dimensional stack IC to transport said light energy to said registers.
Claim 20
Dependent Claim
23 words
A method according to claim 18, wherein said transparent channels are formed in the plane of circuits to be energized in said registers.
Claim 21
Dependent Claim
29 words
A method according to claim 18, wherein said transparent channels are formed to transmit light energy at right angles to planes of circuits to be energized in said registers.
Claim 22
Dependent Claim
35 words
A method according to claim 12, wherein said monocrystalline semiconductor bodies to be connected are formed (1) of semiconductor material for fulfilling mainly electrical functions, and (2) of semiconductor material for fulfilling mainly optical functions.
Claim 23
Dependent Claim
41 words
A method according to claim 21, wherein said semiconductor material for fulfilling mainly optical functions is configured with light-dissipating leads for dissipating light energy to the outside of said semiconductor structure or for internally converting light energy into an electrical signal.
Claim 24
Dependent Claim
25 words
A method according to claim 21, further comprising forming insulating channels in said registers to have a dual function of electrical insulation and light conduction.
Claim 25
Dependent Claim
25 words
A method according to claim 1, wherein said light surface smoothing operation includes smoothing a surface of said electrically insulating layer by removing microscopic unevenness.
Claim 26
Dependent Claim
21 words
A method according to claim 1, wherein said chemical etching operation includes lightly etching a surface of said electrically insulating layer.
Claim 27
Independent Claim
229 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (b) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (c) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, (d) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (e) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350°C., (f) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (g) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns, wherein said monocrystalline semiconductor body includes a highly doped first layer and a weakly doped second layer epitaxially grown on said first layer, and wherein said step of thinning by etching is carried out by an electrochemical etch treatment to etch away completely said first layer, said electrochemical etch treatment being stopped at said second layer.
Claim 28
Independent Claim
229 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (b) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (c) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, (d) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (e) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350°C., (f) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (g) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns, wherein said monocrystalline semiconductor body includes a highly doped first layer and a weakly doped second layer epitaxially grown on said first layer, and wherein said step of thinning by etching is carried out by an electrochemical etch treatment to etch away completely said first layer, said electrochemical etch treatment being stopped at said second layer.
Claim 29
Dependent Claim
21 words
A method according to claim 26, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.
Claim 30
Dependent Claim
21 words
A method according to claim 26, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.
Claim 31
Dependent Claim
16 words
A method according to claim 26, wherein said bonding-activating operation is a light surface smoothing operation.
Claim 32
Dependent Claim
15 words
A method according to claim 26, wherein said bonding-activating operation is a chemical etching operation.
Claim 33
Dependent Claim
49 words
A method according to claim 26, wherein said bonding-activating operation includes the steps of providing a layer of wet chemically spun glass, removing organic components from said layer at a temperature of about 200° C., and densifying said layer to glass at a temperature of at least 800° C.
Claim 34
Independent Claim
226 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) forming said support body by growing a magnetic garnet layer on a first non-magnetic garnet layer, (b) forming a magnetic domain memory or Bloch line memory, (c) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (d) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (e) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, (f) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (g) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350° C., (h) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (i) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns, (j) forming semiconductor elements in said monocrystalline semiconductor body to obtain an electrical circuit for controlling said magnetic domain memory or saiud bloch line memory.
Claim 35
Independent Claim
226 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) forming said support body by growing a magnetic garnet layer on a first non-magnetic garnet layer, (b) forming a magnetic domain memory or Bloch line memory, (c) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (d) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (e) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, (f) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (g) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350° C., (h) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (i) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns, (j) forming semiconductor elements in said monocrystalline semiconductor body to obtain an electrical circuit for controlling said magnetic domain memory or saiud bloch line memory.
Claim 36
Dependent Claim
21 words
A method according to claim 32, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.
Claim 37
Dependent Claim
21 words
A method according to claim 32, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.
Claim 38
Dependent Claim
16 words
A method according to claim 32, wherein said bonding-activating operation is a light surface smoothing operation.
Claim 39
Dependent Claim
15 words
A method according to claim 32, wherein said bonding-activating operation is a chemical etching operation.
Claim 40
Dependent Claim
49 words
A method according to claim 32, wherein said bonding-activating operation includes the steps of providing a layer of wet chemically spun glass, removing organic components from said layer at a temperature of about 200° C., and densifying said layer to glass at a temperature of at least 800° C.
Claim 41
Independent Claim
221 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) forming said support body by growing a magnetic garnet layer on a first non-magnetic garnet layer, (b) forming a magnetic domain memory or Bloch line memory, (c) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (d) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (e) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, (f) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (g) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350° C., (h) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (i) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns, (j) forming semiconductor elements as an electrical memory to provide an interaction between said magnetic memory and said electric memory.
Claim 42
Independent Claim
221 words
A method of manufacturing a semiconductor structure having at least a support body and a monocrystalline semiconductor body, said method comprising the steps of (a) forming said support body by growing a magnetic garnet layer on a first non-magnetic garnet layer, (b) forming a magnetic domain memory or Bloch line memory, (c) providing both said support body and said monocrystalline semiconductor body with at least one flat optically smooth surface by a bulk-reducing polishing operation, (d) providing an electrically insulating layer on the optically smooth surface of at least said monocrystalline semiconductor body, (e) subjecting said electrically insulating layer on at least said monocrystalline semiconductor body to a bonding-activating operation, (f) then contacting at least the optically smooth surface of said support body to said electrically insulating layer on said optically smooth surface of said monocrystalline semiconductor body in a dust-free atmosphere to obtain a mechanical connection, (g) then subjecting the contacted support body and monocrystalline semiconductor body to a heat treatment of at least 350° C., (h) establishing a very firm bond between said support body and said monocrystalline semiconductor body, and (i) thereafter thinning by etching said monocrystalline semiconductor body to a predetermined thickness between 0.05 and 100 microns, (j) forming semiconductor elements as an electrical memory to provide an interaction between said magnetic memory and said electric memory.
Claim 43
Dependent Claim
21 words
A method according to claim 38, wherein said monocrystalline semiconductor body is thinned to a thickness between 0.1 and 1 micron.
Claim 44
Dependent Claim
21 words
A method according to claim 38, wherein said monocrystalline semiconductor body is thinned to a thickness between 1 and 20 microns.
Claim 45
Dependent Claim
16 words
A method according to claim 38, wherein said bonding-activating operation is a light surface smoothing operation.
Claim 46
Dependent Claim
15 words
A method according to claim 38, wherein said bonding-activating operation is a chemical etching operation.
Claim 47
Dependent Claim
49 words
A method according to claim 38, wherein said bonding-activating operation includes the steps of providing a layer of wet chemically spun glass, removing organic components from said layer at a temperature of about 200° C., and densifying said layer to glass at a temperature of at least 800° C.
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