Methods and apparatus for determining the absolute value of the difference between binary operands

Claim 3

A method according to claim 1 in which the adder includes a plurality of bit slices and including the steps of: in each bit slice, providing local carry-in logic for combining a merged propagate signal PIN* from less significant bit slices of the adder, a merged generate signal GIN* from less significant bit slices of the adder and a global carry-in signal CIN* from a carry input to the adder to define a local carry-in logic state; in each bit slice, exclusive-OR-ing a partial sum signal with the invert signal to define a second logic state; and in each bit slice, combining the carry-in logic state with the second logic state to form the sum output logic signal.

Claim 4

A carry-lookahead adder for generating the absolute value of the difference between the values of A and B binary operands, comprising: means defining inputs to the adder for receiving binary operands A and the complement of B; means coupled to the inputs for forming generate, propagate and partial sum logic signals for each bit position; means for combining the generate and propagate logic signals from all less significant bit positions to form a merged carry generate logic signal and a merged carry propagate logic signal for each bit position; first exclusive-OR logic means for combining the partial sum logic signals in each bit position with corresponding merged carry generate and merged carry propagate logic signals to form respective sum bits; means for providing an invert signal indicating that B has a magnitude greater than A; and second exclusive-OR logic means responsive to the invert signal for inverting the sum bits in the event B has a magnitude greater than A.

Claim 5

A carry-lookahead adder for generating the absolute value of the difference between the values of A and B binary operands, comprising: means defining inputs to the adder for receiving binary operands A and the complement of B; means coupled to the inputs for forming generate, propagate and partial sum logic signals for each bit position; means for combining the generate and propagate logic signals from all less significant bit positions to form a merged carry generate logic signal and a merged carry propagate logic signal for each bit position; first exclusive-OR logic means for combining the partial sum logic signals in each bit position with corresponding merged carry generate and merged carry propagate logic signals to form respective sum bits; means for providing an invert signal indicating that B has a magnitude greater than A; and second exclusive-OR logic means responsive to the invert signal for inverting the sum bits in the event B has a magnitude greater than A.

Claim 6

An adder according to claim 3 wherein the second exclusive-OR logic means is integrated within the carry-lookahead adder so as to controllably invert the sum bits without delay.

Claim 7

An adder according to claim 3 including local carry-in logic means in each bit position for generating a respective local carry-in logic signals and wherein the first and second exclusive-OR logic means include, in each bit position: first and second nodes separately biased to a reference voltage source corresponding to a first logic state; means responsive to the carry-in logic means for asserting the first node to a second logic state opposite the first logic state when the local carry-in logic state is true and for asserting the second node to a second logic state opposite the first logic state when the local carry-in logic state is false; exclusive-OR logic means coupled to receive a partial sum signal and the invert signal for asserting the first node to the second logic state when the partial sum signal and the invert signal have the same logic state and for asserting the second node to the second logic state when the partial sum signal and the invert signal have opposite logic states; and output means coupled to the first and second nodes for providing a sum output signal that is false only when both the first and second nodes have the second logic state; the sum output signal being the exclusive-OR logical function of the partial sum signal and the invert signal and the local carry-in logic state.

Claim 8

A carry-lookahead adder having a plurality of bit slices, circuitry for each bit slice comprising: first and second nodes separately biased to a reference voltage source corresponding to a first logic state; carry-in logic means coupled to receive a merged propagate signal PIN* from less significant bit slices of the adder, a merged generate signal GIN* from less significant bit slices of the adder and a global carry-in signal CIN* from a carry input to the adder for determining a local carry-in logic state; means responsive to the carry-in logic means for asserting the first node to a second logic state opposite the first logic state when the local carry-in logic state is true and for asserting the second node to a second logic state opposite the first logic state when the local carry-in logic state is false; exclusive-OR logic means coupled to receive a partial sum signal PO* and an invert signal INV@2 for asserting the first node to the second logic state when PO* and INV@2 have the same logic state and for asserting the second node to the second logic state when PO* and INV@2 have opposite logic states; and output means coupled to the first and second nodes for providing a sum output signal SO that is false only when both the first and second nodes have the second logic state, SO being the exclusive-OR logical function of PO* and INV@2 logic signals and the local carry-in logic state.

Claim 9

A carry-lookahead adder having a plurality of bit slices, circuitry for each bit slice comprising: first and second nodes separately biased to a reference voltage source corresponding to a first logic state; carry-in logic means coupled to receive a merged propagate signal PIN* from less significant bit slices of the adder, a merged generate signal GIN* from less significant bit slices of the adder and a global carry-in signal CIN* from a carry input to the adder for determining a local carry-in logic state; means responsive to the carry-in logic means for asserting the first node to a second logic state opposite the first logic state when the local carry-in logic state is true and for asserting the second node to a second logic state opposite the first logic state when the local carry-in logic state is false; exclusive-OR logic means coupled to receive a partial sum signal PO* and an invert signal INV@2 for asserting the first node to the second logic state when PO* and INV@2 have the same logic state and for asserting the second node to the second logic state when PO* and INV@2 have opposite logic states; and output means coupled to the first and second nodes for providing a sum output signal SO that is false only when both the first and second nodes have the second logic state, SO being the exclusive-OR logical function of PO* and INV@2 logic signals and the local carry-in logic state.

Claim 10

A carry-lookahead adder circuit for generating the absolute value of the difference between the values of A and B binary operands, the adder circuit comprising: a plurality of N-bit adder slices, where N is a predetermined nonzero positive integer, circuitry for each N-bit adder slice comprising: means defining inputs to the adder slice circuit for receiving a respective N-bit slice of binary operands A and the complement of B; means coupled to the inputs for forming generate, propagate and partial sum logic signals; means for combining the generate and propagate logic signals from all less significant adder slice circuits to form a merged generate logic signal and a merged propagate logic signal; first XOR logic means for combining the partial sum logic signals with corresponding merged generate and merged propagate logic signals to form sum bits; and second XOR logic means for inverting the sum bits; the adder further comprising means for providing an invert signal; and the second XOR logic means in each adder slice circuit being responsive to the invert signal.

Claim 11

A carry-lookahead adder circuit for generating the absolute value of the difference between the values of A and B binary operands, the adder circuit comprising: a plurality of N-bit adder slices, where N is a predetermined nonzero positive integer, circuitry for each N-bit adder slice comprising: means defining inputs to the adder slice circuit for receiving a respective N-bit slice of binary operands A and the complement of B; means coupled to the inputs for forming generate, propagate and partial sum logic signals; means for combining the generate and propagate logic signals from all less significant adder slice circuits to form a merged generate logic signal and a merged propagate logic signal; first XOR logic means for combining the partial sum logic signals with corresponding merged generate and merged propagate logic signals to form sum bits; and second XOR logic means for inverting the sum bits; the adder further comprising means for providing an invert signal; and the second XOR logic means in each adder slice circuit being responsive to the invert signal.