Abstract The present invention provides a radar simulation system with at least two counters. The first counter is a coarse counter 20/30 that counts a transmit pulse interpulse periods to provide a coarse return delay at the beginning of a radar look. The second counter is a fine counter 22/36 which counts, after the coarse counter has counted down to zero, from each subsequent transmit pulse to the time for the return pulse. Once the coarse counter has finished counting, the fine counter, which can be reset and reloaded during the look responsive to each transmit pulse, can provide return targets repeating at the same distance at the pulse repetition frequency. A cyclic counter 24 can also be added that produces the return pulses by cyclically counting the interpulse period one the fine counter has timed out. If the cyclic counter is used the fine counter is not reloaded during the look. If the target moves more than the range resolution of the radar during the radar look, a phase-in counter 70 and secondary return counter 66 adjust the delay of the return pulses to simulate target movement during the radar look.
A target simulator trigger signal generator, comprising: coarse delay means for providing a coarse delay equal to a number of interpulse periods occurring during a delay required for a target return pulse to be simulated; and fine delay means, actuated by said coarse delay means, for providing a trigger signal for the return pulse after a fine delay equal to a difference between the coarse delay and the delay required for the return pulse.
Claim 2
Dependent Claim
74 words
A target simulator trigger signal generator, comprising: coarse delay means for providing a coarse delay equal to a number of interpulse periods occurring during a delay required for a target return pulse to be simulated; and fine delay means, actuated by said coarse delay means, for providing a trigger signal for the return pulse after a fine delay equal to a difference between the coarse delay and the delay required for the return pulse.
Claim 3
Dependent Claim
35 words
A target simulator trigger signal generator as recited in claim 1, further comprising cyclic means, actuated by said fine delay means, for cyclically producing the return pulse with a period equal to the interpulse period.
Claim 4
Dependent Claim
35 words
A target simulator trigger signal generator as recited in claim 1, further comprising target range change means for chaning the coarse and/or the fine delay when a target to be simulated changes a simulated range.
Claim 5
Dependent Claim
29 words
A target simulator trigger signal generator as recited in claim 3, wherein said change means includes phase means for determining a time for changing the coarse and fine delays.
Claim 6
Dependent Claim
103 words
A target simulator trigger signal generator, comprising: a coarse counter down counting a quotient of a division of a target range by an interpulse period responsive to a radar transmit pulse; a fine counter connected to said coarse counter and down counting a remainder of the division when said coarse counter reaches zero responsive to a radar system clock; and a cyclic counter connected to said fine counter, cyclically down counting the interpulse period responsive to the radar system clock when said fine counter reaches zero and producing a trigger signal for a target return pulse each time said cyclic counter reaches zero.
Claim 7
Dependent Claim
103 words
A target simulator trigger signal generator, comprising: a coarse counter down counting a quotient of a division of a target range by an interpulse period responsive to a radar transmit pulse; a fine counter connected to said coarse counter and down counting a remainder of the division when said coarse counter reaches zero responsive to a radar system clock; and a cyclic counter connected to said fine counter, cyclically down counting the interpulse period responsive to the radar system clock when said fine counter reaches zero and producing a trigger signal for a target return pulse each time said cyclic counter reaches zero.