US4049953A
Expired / Lapsed
US
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Complex pulse repetition frequency generator
Assignee: United States Department of the Navy
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Filing: 1976-06-24
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Granted: 1977-09-20
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Expires: 1996-06-24
Abstract
Abstract A complex pulse repetition frequency generator for producing a pulse repeion frequency (PRF) signal having programmable stagger intervals. The device consists of a clock for selecting one of a series of standard clock pulses which are used to increment a counter. A comparator compares the accumlated clock pulses with a stagger data output signal produced by a data memory source. When the outputs are equal, the comparator produces a PRF output pulse. Two data memory bands are provided; a random access memory in which stagger data can be programmed by a series of switches, and a preprogrammed read-only memory. Address counters are used with each memory unit and provide capability for addressing selected memory locations from the data memory sources. A pulse width generator allows the operator to vary the pulse width and utilizes an injection lock oscillator to prevent jitter whenever a standard clock pulse is used which is not an even multiple of a hundred nanoseconds.
Inventors
- 👤 Albert B. Evans, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:28
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/06; G01S13/08; G01S13/10; G01S13/22; G01S13/225; G01S13/12; G01S7/00; G01S7/02; G01S7/36; G01S7/40; G01S7/4052; G01S7/4082
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
112 words
A complex pulse repetition frequency generator for generating a pulse repetition frequency signal having programmable stagger intervals comprising: a. clock means for generating a plurality of standard clock frequency signals; b. memory address control means for generating a plurality of memory address signal sequences, each said memory address signal sequence having a start address and a stop address; c. data memory means for producing a series of stagger data pulses in response to each said memory address signal sequence; and, d. digitally programmable delay generating means for producing a pulse repetition frequency signal having stagger intervals generated in response to said series of stagger data pulses and to said clock frequency signals.
Claim 2
Dependent Claim
112 words
A complex pulse repetition frequency generator for generating a pulse repetition frequency signal having programmable stagger intervals comprising: a. clock means for generating a plurality of standard clock frequency signals; b. memory address control means for generating a plurality of memory address signal sequences, each said memory address signal sequence having a start address and a stop address; c. data memory means for producing a series of stagger data pulses in response to each said memory address signal sequence; and, d. digitally programmable delay generating means for producing a pulse repetition frequency signal having stagger intervals generated in response to said series of stagger data pulses and to said clock frequency signals.
Claim 3
Dependent Claim
21 words
The generator of claim 1 further comprising pulse width generating means for controlling pulse width of said pulse repetition frequency signal.
Claim 4
Dependent Claim
49 words
The generator of claim 1 wherein said digitally programmable delay generating means comprises: a. counter means for producing an output signal representative of an accumulated count of said clock frequency signals; b. means for comparing said accumulated count from said counter means with said series of stagger data pulses.
Claim 5
Dependent Claim
33 words
The generator of claim 1 wherein said memory address control means comprises address counter means for accumulating pulses from said pulse repetition frequency signal to generate said plurality of memory address signal sequences.
Claim 6
Dependent Claim
28 words
The generator of claim 4 wherein said memory address control means further comprises means for detecting a preselected address signal to reset said address counter means to zero.
Claim 7
Dependent Claim
36 words
The generator of claim 5 wherein said means for detecting a preselected address signal comprises: a. means for generating an address stop signal; b. means for comparing said address stop signal with said memory address signal.
Claim 8
Dependent Claim
15 words
The generator of claim 1 wherein said data memory means comprises a programmable read-only memory.
Claim 9
Dependent Claim
69 words
The generator of claim 2 wherein said pulse width generating means comprises: a. a pulse width data generator; b. injection oscillation means for producing clock pulses in synchronization with said standard clock frequency signals; c. means for counting said clock pulses; and, d. means for comparing said counted clock pulses with a data signal generated by said pulse width data generator to produce a reset pulse in a flip-flop.
Claim 10
Dependent Claim
26 words
The generator of claim 1 wherein said control means further comprises means for switching from one memory address signal sequence to another memory address signal sequence.
Claim 11
Dependent Claim
35 words
The generator of claim 9 wherein said switching means, when switching from one memory address signal sequence to another memory address signal sequence, switches to said start address of said another memory address signal sequence.
Claim 12
Dependent Claim
97 words
The generator of claim 9 wherein said switch means includes: a. a plurality of start address switches, one each for a respective memory address signal sequence; b. a plurality of stop address switches, one each for a respective memory address signal sequence; c. a plurality of comparators, responsive to a respective stop address switch and to said memory address signal sequences, for generating a control signal when said respective memory address signal sequence terminates; d. address counter means, responsive to said start address switches and to said control signal, for generating the next memory address signal sequence.
Claim 13
Dependent Claim
37 words
The generator of claim 11 further comprising multiposition frame switch means responsive to said control signal and to said address counter means for providing manual switching to said start address of a specific memory address signal sequence.
Claim 14
Dependent Claim
19 words
The generator of claim 1 wherein said plurality of memory address signal sequences include two memory address signal sequences.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-19 | 1981-03-21 | 1981-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-19 | 1985-03-21 | 1985-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-19 | 1989-03-21 | 1989-09-20 | $7700.00 | Window Closed / Lapsed |