US4982115A
Expired / Lapsed
US
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Digital signal direction detection circuit
Assignee: Mindspeed Technologies LLC
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Filing: 1989-02-02
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Granted: 1991-01-01
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Expires: 2009-02-02
Abstract
Abstract A digital circuit includes two digital signal sources, each having an output terminal connected to corresponding bus portions. Logic connects the two bus portions for propagating a signal pulse on one of the bus portions onto the other of the bus portion, and produces a digital indication signal signifying which of the signal sources generated the signal pulse. The logic includes logic gates, each having a first input connected to its corresponding bus portion, an output terminal connected to the indicator output, and a second input terminal connected to the output terminal of the opposite logic gate. The output of each logic gate also controls the connection of the other bus portion to a voltage source to bring that bus portion to the active state in response to the other bus portion being rendered active by its associated signal source.
Inventors
- 👤 Waitak P. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:11
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/026
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
296 words
A digital circuit comprising: first and second digital signal sources, each having an output terminal; a first bus portion connected to the output terminal of said first signal source; a second bus portion connected to the output terminal of said second signal source; digital logic connecting said first and second bus portions for propagating a signal pulse on one of said bus portions onto the other of said bus portions, and for producing an indication signal signifying which of said signal sources generated the signal pulse, wherein said digital logic comprises: a first logic gate having first and second input terminals and an output terminal, wherein said first input terminal is connected to said first bus portion; a second logic gate having first and second input terminals and an output terminal, wherein said first input terminal is connected to said second bus portion, said second input terminal is connected to said output terminal of said first logic gate, and said output terminal of said second logic gate is connected to said second input terminal of said first logic gate; a first indicator output terminal connected to said output terminal of said first logic gate; a second indicator output terminal connected to said output terminal of said second logic gate; a first voltage source connected to said first and second bus portions; a second voltage source; a first switch for selectively connecting said second voltage source to said first bus portion; and a second switch for selectively connecting said second voltage source to said second bus portion; wherein: said output terminal of said first logic gate is connected to said second switch to control said second switch; and said output terminal of said second logic gate is connected to said first switch to control said first switch.
Claim 2
Dependent Claim
296 words
A digital circuit comprising: first and second digital signal sources, each having an output terminal; a first bus portion connected to the output terminal of said first signal source; a second bus portion connected to the output terminal of said second signal source; digital logic connecting said first and second bus portions for propagating a signal pulse on one of said bus portions onto the other of said bus portions, and for producing an indication signal signifying which of said signal sources generated the signal pulse, wherein said digital logic comprises: a first logic gate having first and second input terminals and an output terminal, wherein said first input terminal is connected to said first bus portion; a second logic gate having first and second input terminals and an output terminal, wherein said first input terminal is connected to said second bus portion, said second input terminal is connected to said output terminal of said first logic gate, and said output terminal of said second logic gate is connected to said second input terminal of said first logic gate; a first indicator output terminal connected to said output terminal of said first logic gate; a second indicator output terminal connected to said output terminal of said second logic gate; a first voltage source connected to said first and second bus portions; a second voltage source; a first switch for selectively connecting said second voltage source to said first bus portion; and a second switch for selectively connecting said second voltage source to said second bus portion; wherein: said output terminal of said first logic gate is connected to said second switch to control said second switch; and said output terminal of said second logic gate is connected to said first switch to control said first switch.
Claim 3
Dependent Claim
207 words
A digital signal direction detection circuit comprising: a first circuit input terminal; a second circuit input terminal; a first logic gate having a first input terminal, a second input terminal, and an output terminal; a second logic gate having a first input terminal, a second input terminal, and an output terminal; wherein: said output terminal of said first logic gate is connected to a first indication line; said output terminal of said second logic gate is connected to a second indication line; said first input terminal of said first logic gate is connected to said first circuit input terminal, to a first voltage source, and, through a first FET switch, to a second voltage source; said first input terminal of said second logic gate is connected to said second circuit input terminal, to said first voltage source, and, through a second FET switch, to said second voltage source; said second input terminal of said first logic gate is connected to the gate of said first FET switch and to said output terminal of said second logic gate; and said second input terminal of said second logic gate is connected to the gate of said second FET switch and to said output terminal of said first logic gate.
Claim 4
Dependent Claim
207 words
A digital signal direction detection circuit comprising: a first circuit input terminal; a second circuit input terminal; a first logic gate having a first input terminal, a second input terminal, and an output terminal; a second logic gate having a first input terminal, a second input terminal, and an output terminal; wherein: said output terminal of said first logic gate is connected to a first indication line; said output terminal of said second logic gate is connected to a second indication line; said first input terminal of said first logic gate is connected to said first circuit input terminal, to a first voltage source, and, through a first FET switch, to a second voltage source; said first input terminal of said second logic gate is connected to said second circuit input terminal, to said first voltage source, and, through a second FET switch, to said second voltage source; said second input terminal of said first logic gate is connected to the gate of said first FET switch and to said output terminal of said second logic gate; and said second input terminal of said second logic gate is connected to the gate of said second FET switch and to said output terminal of said first logic gate.
Claim 5
Dependent Claim
47 words
The digital signal direction detection circuit of claim 2, wherein: said first and second logic gates are NOR gates; said first voltage source is at approximately +5 volts; said second voltage source is at approximately ground potential; and said first and second FET switches are enhancement-mode FETs.
Claim 6
Dependent Claim
47 words
The digital signal direction detection circuit of claim 2, wherein: said first and second logic gates are NAND gates; said first voltage source is at approximately ground potential; said second voltage source is at approximately +5 volts; and said first and second FET switches are depletion-mode FETs.
Claim 7
Dependent Claim
202 words
A digital signal direction detection circuit comprising: a first circuit input terminal; a second circuit input terminal; a first logic gate having a first input terminal connected to said first circuit input terminal, a second input terminal, and an output terminal; a second logic gate having a first input terminal connected to said second circuit input terminal, a second input terminal connected to said output terminal of said first logic gate, and an output terminal connected to said second input terminal of said first logic gate; a first source of a first electric potential connected to said first and second circuit input terminals; a second source of a second electric potential; a first switch connected between said second electric potential source and said first circuit input terminal and having a control terminal connected to said output terminal of said second logic gate for selectively connecting said second electric potential source and said first circuit input terminal; and a second switch connected between said second electric potential source and said second circuit input terminal and having a control terminal connected to said output terminal of said first logic gate for selectively connecting said second electric potential source and said second circuit input terminal.
Claim 8
Dependent Claim
202 words
A digital signal direction detection circuit comprising: a first circuit input terminal; a second circuit input terminal; a first logic gate having a first input terminal connected to said first circuit input terminal, a second input terminal, and an output terminal; a second logic gate having a first input terminal connected to said second circuit input terminal, a second input terminal connected to said output terminal of said first logic gate, and an output terminal connected to said second input terminal of said first logic gate; a first source of a first electric potential connected to said first and second circuit input terminals; a second source of a second electric potential; a first switch connected between said second electric potential source and said first circuit input terminal and having a control terminal connected to said output terminal of said second logic gate for selectively connecting said second electric potential source and said first circuit input terminal; and a second switch connected between said second electric potential source and said second circuit input terminal and having a control terminal connected to said output terminal of said first logic gate for selectively connecting said second electric potential source and said second circuit input terminal.
Claim 9
Dependent Claim
83 words
The circuit of claim 5 wherein: said first switch is an FET having its conduction path connected between said second source of electric potential and said first circuit input terminal, and having its gate connected to said output terminal of said second logic gate; and said second switch is an FET having its conduction path connected between said second source of electric potential and said second circuit input terminal and having its gate connected to said output terminal of said first logic gate.
Claim 10
Dependent Claim
44 words
The circuit of claim 6, wherein: said first and second logic gates are NOR gates; said first source of electric potential is a source of relatively high electric potential; and said second source of electric potential is a source of relatively low electric potential.
Claim 11
Dependent Claim
44 words
The circuit of claim 6, wherein: said first and second logic gates are NAND gates; said first source of electric potential is a source of relatively low electric potential; and said second source of electric potential is a source of relatively high electric potential.
Claim 12
Dependent Claim
83 words
The circuit of claim 6, wherein: said first switch is an FET having its conduction path connected between said second source of electric potential and said first circuit input terminal, and having its gate connected to said output terminal of said second logic gate; and said second switch is an FET having its conduction path connected between said second source of electric potential and said second circuit input terminal and having its gate connected to said output terminal of said first logic gate.
Claim 13
Dependent Claim
40 words
The circuit of claim 9, wherein: said first and second logic gates are NOR gates; said first voltage source is a source of relatively high electric potential; and said second voltage source is a source of relatively low electric potential.
Claim 14
Dependent Claim
40 words
The circuit of claim 9, wherein: said first and second logic gates are NAND gates; said first voltage source is a source of relatively low electric potential; and said second voltage source is a source of relatively high electric potential.
References Cited (Backward Citations)
US1191152A
Cited
US3317668A
Cited
US3832703A
Cited
US3769525A
Cited
US4154978A
Cited
US4419592A
Cited
US4390990A
Cited
US4680491A
Cited
US4713557A
Cited
US4624006A
Cited
US4714802A
Cited
US4774422A
Cited
US4835418A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-31 | 1994-07-02 | 1995-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-31 | 1998-07-02 | 1999-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-31 | 2002-07-02 | 2003-01-01 | $7700.00 | Window Closed / Lapsed |