US4982108A — Low current CMOS translator circuit

Claim 1

Independent Claim 186 words

A low current translator, for translating a square wave input signal having a first voltage range to a translated square wave output signal having a second voltage range while preserving a duty cycle associated with said input signal, comprising: (a) at least one inverting stage means, each one for providing an output signal at a second voltage range which is an inverted and translated version of a square wave input signal at a first voltage range applied thereto; (b) current supplying means for supplying current to each of said inverting stage means; (c) at least one capacitor means, each one coupled to a respective one of said inverting stage means, as well as to said current supplying means, for storing and developing a supply voltage for a respective one of said inverting stage means; and (d) voltage clamping means, coupled to said at least one inverting stage means, said current supplying means and to said at least one capacitor means as well as to each of a second supply voltage for clamping said input signal to a second voltage range limited by said second supply voltage.

Claim 2

Dependent Claim 186 words

A low current translator, for translating a square wave input signal having a first voltage range to a translated square wave output signal having a second voltage range while preserving a duty cycle associated with said input signal, comprising: (a) at least one inverting stage means, each one for providing an output signal at a second voltage range which is an inverted and translated version of a square wave input signal at a first voltage range applied thereto; (b) current supplying means for supplying current to each of said inverting stage means; (c) at least one capacitor means, each one coupled to a respective one of said inverting stage means, as well as to said current supplying means, for storing and developing a supply voltage for a respective one of said inverting stage means; and (d) voltage clamping means, coupled to said at least one inverting stage means, said current supplying means and to said at least one capacitor means as well as to each of a second supply voltage for clamping said input signal to a second voltage range limited by said second supply voltage.

Claim 3

Dependent Claim 180 words

A low current translator, for translating a square wave input signal having a first voltage range to a translated square wave output signal having a second voltage range while preserving a duty cycle associated with said input signal, comprising: (a) a plurality of cascaded inverting stage means, each for providing an output signal at a second voltage range which is an inverted and translated version of an input signal at a first voltage range applied thereto; (b) current supplying means for supplying current to each of said plurality of cascaded inverting stage means; (c) a plurality of capacitor means, each one coupled to a respective one of said plurality of inverting stage means, as well as to said current supplying means, of storing and developing a supply voltage for a second voltage range for a respective one of said inverting stage means; and (d) at least one voltage clamping means, coupled to at least one of said plurality of cascaded inverting stage means, for clamping said input signal to a second supply voltage that corresponds to said second voltage range.

Claim 4

Dependent Claim 180 words

A low current translator, for translating a square wave input signal having a first voltage range to a translated square wave output signal having a second voltage range while preserving a duty cycle associated with said input signal, comprising: (a) a plurality of cascaded inverting stage means, each for providing an output signal at a second voltage range which is an inverted and translated version of an input signal at a first voltage range applied thereto; (b) current supplying means for supplying current to each of said plurality of cascaded inverting stage means; (c) a plurality of capacitor means, each one coupled to a respective one of said plurality of inverting stage means, as well as to said current supplying means, of storing and developing a supply voltage for a second voltage range for a respective one of said inverting stage means; and (d) at least one voltage clamping means, coupled to at least one of said plurality of cascaded inverting stage means, for clamping said input signal to a second supply voltage that corresponds to said second voltage range.

Claim 5

Dependent Claim 139 words

A low current, squaring translator means, for squaring and then translating an internally generated sinusoidal signal to provide a translated square wave output signal, comprising: (a) low current inverting means for providing an inverting gain stage for generating a sinusoidal signal coupled to an included first current supplying means and first capacitor means for developing a first supply voltage therein; (b) squaring means coupled to said low current inverting means and having a first internal supply node that couples to an included first capacitor means, said squaring means for squaring said sinusoidal signal to establish a square wave signal that exhibits a precise duty cycle with low noise; and (c) low current translating means for translating said square wave signal coupled thereto, to provide a translated square wave output signal to maintain a precise duty cycle with low noise.

Claim 6

Dependent Claim 139 words

A low current, squaring translator means, for squaring and then translating an internally generated sinusoidal signal to provide a translated square wave output signal, comprising: (a) low current inverting means for providing an inverting gain stage for generating a sinusoidal signal coupled to an included first current supplying means and first capacitor means for developing a first supply voltage therein; (b) squaring means coupled to said low current inverting means and having a first internal supply node that couples to an included first capacitor means, said squaring means for squaring said sinusoidal signal to establish a square wave signal that exhibits a precise duty cycle with low noise; and (c) low current translating means for translating said square wave signal coupled thereto, to provide a translated square wave output signal to maintain a precise duty cycle with low noise.

Claim 7

Dependent Claim 32 words

The low current squaring translator means according to claim 3, wherein said inverting stage means is coupled to a crystal and said first capacitor means comprises a capacitor of about 15 picofarads.

Claim 8

Dependent Claim 30 words

The low current squaring translator means according to claim 3, wherein said low current inverting means is constructed and arranged for use with a crystal to generate a sinusoidal signal.

Claim 9

Dependent Claim 30 words

The low current squaring translator means according to claim 5, including a programmable current source that supplies a level of current between about 30-300 ampers when operating at 10-20 MHz.

Claim 10

Dependent Claim 21 words

The low current squaring translator means according to claim 3, wherein said first current supplying means comprises a programmable current source.

Claim 11

Dependent Claim 32 words

A low current squaring translator means according to claim 3, wherein said first capacitor of said squaring means comprises a capacitor of at least 5 picofarads coupled to said first supply node.

Claim 12

Dependent Claim 94 words

The low current squaring translator means according to claim 3, wherein said squaring means comprises: (b1) a first squaring inverter for squaring a first signal to provide an intermediate signal; (b2) a second squaring inverter coupled to said first squaring inverter, for squaring said intermediate signal to provide a square wave output signal; and (b3) supply buffer means coupled to said first supply node of said low current inverting means, for supplying a buffered supply voltage to said first supply node of said squaring means that couples to said first and second squaring inverters.

Claim 13

Dependent Claim 26 words

The low current squaring translator means according to claim 9, wherein said first and said second squaring means each comprise a pair of complementary CMOS devices.

Claim 14

Dependent Claim 19 words

The low current squaring translator means according to claim 9, wherein said supply buffer means comprises a voltage follower.

Claim 15

Dependent Claim 74 words

The low current squaring translator means according to claim 3, wherein said low current translating means comprises: (c1) a plurality of cascaded inverting stages; (c2) a current source coupled to said plurality of cascaded inverting stages; (c3) a plurality of capacitors, each one coupled to a respective one of said plurality of cascaded inverting stages; and (c4) at least one voltage clamp coupled to at least one of said plurality of cascaded inverting stages.

Claim 16

Dependent Claim 49 words

The low current squaring translator means according to claim 12, wherein said plurality of cascaded inverting stages includes at least a first inverting stage and a second inverting stage, such that any skew in duty cycle exhibited by said first inverting stage is negated by said second inverting stage.

Claim 17

Dependent Claim 127 words

A low current translating means, for translating a square wave input signal having a first voltage range to a translated square wave output signal having a second voltage range while preserving a duty cycle associated with said input signal, comprising: (a) at least one inverting stage means, each one for providing an output signal which is an inverted and translated version of a square wave input signal applied thereto; (b) current supplying means for supplying current to each of said inverting stage means; and (c) at least one capacitor means, each one coupled to a respective one of said inverting stage means, as well as to said current said supplying means, for storing and developing a supply voltage for a respective one of said inverting stage means.

Claim 18

Dependent Claim 127 words

A low current translating means, for translating a square wave input signal having a first voltage range to a translated square wave output signal having a second voltage range while preserving a duty cycle associated with said input signal, comprising: (a) at least one inverting stage means, each one for providing an output signal which is an inverted and translated version of a square wave input signal applied thereto; (b) current supplying means for supplying current to each of said inverting stage means; and (c) at least one capacitor means, each one coupled to a respective one of said inverting stage means, as well as to said current said supplying means, for storing and developing a supply voltage for a respective one of said inverting stage means.

Claim 19

Dependent Claim 21 words

The low current translating means according to claim 14, wherein said inverting stage means comprises a pair of complimentary CMOS devices.

Claim 20

Dependent Claim 20 words

The low current translating means according to claim 14, wherein said current supplying means supplies a fixed amount of current.

Claim 21

Dependent Claim 30 words

The low current translating means according to claim 14, wherein said current supplying means supplies a constant current fixed to a level between 3.0-13.5 microamperes when operating at 10-20 megahertz.

Claim 22

Dependent Claim 20 words

The low current translating means according to claim 14, wherein said current supplying means supplies a variable amount of current.

Claim 23

Dependent Claim 33 words

The low current translating means according to claim 14, wherein said current supplying means supplies a constant current programmable to a level between about 3.0-13.5 microamperes utilizing a plurality of equal-sized programmable steps.

Claim 24

Dependent Claim 23 words

The low current translating means according to claim 14, wherein said at least one capacitor means comprises a capacitor of about 5 picofarads.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1993-12-31	1994-07-02	1995-01-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1997-12-31	1998-07-02	1999-01-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2001-12-31	2002-07-02	2003-01-01	$7700.00	Window Closed / Lapsed

Low current CMOS translator circuit

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